Fixed spelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8588 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 17 insertions, 17 deletions

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 392ae04d68..cf4f294155 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
   if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
     return false;
   
-  // Finally, if the instruction preceeds the branch, we make sure the
+  // Finally, if the instruction precedes the branch, we make sure the
   // instruction can be reordered relative to the branch.  We simply check
   // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
   // 
@@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S,
 		     bool nodeIsPredecessor)
 {
   if (nodeIsPredecessor) {
-    // If node is in the same basic block (i.e., preceeds brNode),
+    // If node is in the same basic block (i.e., precedes brNode),
     // remove it and all its incident edges from the graph.  Make sure we
     // add dummy edges for pred/succ nodes that become entry/exit nodes.
     graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
diff --git a/lib/CodeGen/InstrSelection/InstrForest.cpp b/lib/CodeGen/InstrSelection/InstrForest.cpp
index ceaefd8441..f4736b59ea 100644
--- a/lib/CodeGen/InstrSelection/InstrForest.cpp
+++ b/lib/CodeGen/InstrSelection/InstrForest.cpp
@@ -4,7 +4,7 @@
 //  tree if one or more of them might be potentially combined into a single
 //  complex instruction in the target machine.
 //  Since this grouping is completely machine-independent, we do it as
-//  aggressive as possible to exploit any possible taret instructions.
+//  aggressive as possible to exploit any possible target instructions.
 //  In particular, we group two instructions O and I if:
 //      (1) Instruction O computes an operand used by instruction I,
 //  and (2) O and I are part of the same basic block,
diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp
index 49a599f548..ae910b8921 100644
--- a/lib/CodeGen/InstrSelection/InstrSelection.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp
@@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi,
 {
   mcfi.addTemp(this);
 
-  Operands.push_back(Use(s1, this));  // s1 must be nonnull
+  Operands.push_back(Use(s1, this));  // s1 must be non-null
   if (s2) {
     Operands.push_back(Use(s2, this));
   }
@@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
   MachineFunction &MF = MachineFunction::get(BB->getParent());
 
   // FIXME: if PHI instructions existed in the machine code, this would be
-  // unnecesary.
+  // unnecessary.
   MachineBasicBlock *MBB = 0;
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
     if (I->getBasicBlock() == BB) {
@@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
 	}
     }
   
-  // Finally, do any postprocessing on this node after its children
+  // Finally, do any post-processing on this node after its children
   // have been translated
   // 
   if (treeRoot->opLabel != VRegListOp)
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 248adc2d4d..c8e930e7d4 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -127,7 +127,7 @@ MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
 }
 
 
-// Subsitute all occurrences of Value* oldVal with newVal in all operands
+// Substitute all occurrences of Value* oldVal with newVal in all operands
 // and all implicit refs.
 // If defsOnly == true, substitute defs only.
 unsigned
@@ -140,7 +140,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
   
   unsigned numSubst = 0;
 
-  // Subsitute operands
+  // Substitute operands
   for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
     if (*O == oldVal)
       if (!defsOnly ||
@@ -153,7 +153,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
       else
         someArgsWereIgnored = true;
 
-  // Subsitute implicit refs
+  // Substitute implicit refs
   for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
     if (getImplicitRef(i) == oldVal)
       if (!defsOnly ||
@@ -301,7 +301,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
       OS << "<def>";
   }
     
-  // code for printing implict references
+  // code for printing implicit references
   if (getNumImplicitRefs()) {
     OS << "\tImplicitRefs: ";
     for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
@@ -330,7 +330,7 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
       os << "<d&u>";
   }
   
-  // code for printing implict references
+  // code for printing implicit references
   unsigned NumOfImpRefs = MI.getNumImplicitRefs();
   if (NumOfImpRefs > 0) {
     os << "\tImplicit: ";
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 392ae04d68..cf4f294155 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
   if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
     return false;
   
-  // Finally, if the instruction preceeds the branch, we make sure the
+  // Finally, if the instruction precedes the branch, we make sure the
   // instruction can be reordered relative to the branch.  We simply check
   // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
   // 
@@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S,
 		     bool nodeIsPredecessor)
 {
   if (nodeIsPredecessor) {
-    // If node is in the same basic block (i.e., preceeds brNode),
+    // If node is in the same basic block (i.e., precedes brNode),
     // remove it and all its incident edges from the graph.  Make sure we
     // add dummy edges for pred/succ nodes that become entry/exit nodes.
     graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
diff --git a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp
index ceaefd8441..f4736b59ea 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp
@@ -4,7 +4,7 @@
 //  tree if one or more of them might be potentially combined into a single
 //  complex instruction in the target machine.
 //  Since this grouping is completely machine-independent, we do it as
-//  aggressive as possible to exploit any possible taret instructions.
+//  aggressive as possible to exploit any possible target instructions.
 //  In particular, we group two instructions O and I if:
 //      (1) Instruction O computes an operand used by instruction I,
 //  and (2) O and I are part of the same basic block,
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
index 49a599f548..ae910b8921 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
@@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi,
 {
   mcfi.addTemp(this);
 
-  Operands.push_back(Use(s1, this));  // s1 must be nonnull
+  Operands.push_back(Use(s1, this));  // s1 must be non-null
   if (s2) {
     Operands.push_back(Use(s2, this));
   }
@@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
   MachineFunction &MF = MachineFunction::get(BB->getParent());
 
   // FIXME: if PHI instructions existed in the machine code, this would be
-  // unnecesary.
+  // unnecessary.
   MachineBasicBlock *MBB = 0;
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
     if (I->getBasicBlock() == BB) {
@@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
 	}
     }
   
-  // Finally, do any postprocessing on this node after its children
+  // Finally, do any post-processing on this node after its children
   // have been translated
   // 
   if (treeRoot->opLabel != VRegListOp)