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| author | Joey Gouly <joey.gouly@gmail.com> | 2014-05-03 17:27:06 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@gmail.com> | 2014-05-03 17:27:06 +0000 |
| commit | 72e96a51bffcda773a9b8c11789a7018ea72c768 (patch) | |
| tree | 38cf006e3bbf952d6b5fa84870abfed9729240f8 | |
| parent | 81f28f603ac31349643d132e50768b062d7675a2 (diff) | |
| download | llvm-72e96a51bffcda773a9b8c11789a7018ea72c768.tar.gz llvm-72e96a51bffcda773a9b8c11789a7018ea72c768.tar.bz2 llvm-72e96a51bffcda773a9b8c11789a7018ea72c768.tar.xz | |
[ARM64] Correctly select ANDWri in FastISel.
http://reviews.llvm.org/D3598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207917 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM64/ARM64FastISel.cpp | 19 | ||||
| -rw-r--r-- | test/CodeGen/ARM64/fast-isel-fcmp.ll | 2 |
2 files changed, 14 insertions, 7 deletions
diff --git a/lib/Target/ARM64/ARM64FastISel.cpp b/lib/Target/ARM64/ARM64FastISel.cpp index c43f2af15b..1af5073909 100644 --- a/lib/Target/ARM64/ARM64FastISel.cpp +++ b/lib/Target/ARM64/ARM64FastISel.cpp @@ -577,7 +577,8 @@ bool ARM64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr, // Loading an i1 requires special handling. if (VTIsi1) { - unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass); + MRI.constrainRegClass(ResultReg, &ARM64::GPR32RegClass); + unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri), ANDReg) .addReg(ResultReg) @@ -665,7 +666,8 @@ bool ARM64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr, // Storing an i1 requires special handling. if (VTIsi1) { - unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass); + MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass); + unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri), ANDReg) .addReg(SrcReg) @@ -788,7 +790,8 @@ bool ARM64FastISel::SelectBranch(const Instruction *I) { CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true, ARM64::sub_32); - unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass); + MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass); + unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri), ANDReg) .addReg(CondReg) @@ -1030,7 +1033,9 @@ bool ARM64FastISel::SelectSelect(const Instruction *I) { if (FalseReg == 0) return false; - unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass); + + MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass); + unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri), ANDReg) .addReg(CondReg) @@ -1669,8 +1674,9 @@ bool ARM64FastISel::SelectTrunc(const Instruction *I) { // Issue an extract_subreg to get the lower 32-bits. unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true, ARM64::sub_32); + MRI.constrainRegClass(Reg32, &ARM64::GPR32RegClass); // Create the AND instruction which performs the actual truncation. - unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass); + unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri), ANDReg) .addReg(Reg32) @@ -1691,7 +1697,8 @@ unsigned ARM64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) { DestVT = MVT::i32; if (isZExt) { - unsigned ResultReg = createResultReg(&ARM64::GPR32RegClass); + MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass); + unsigned ResultReg = createResultReg(&ARM64::GPR32spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri), ResultReg) .addReg(SrcReg) diff --git a/test/CodeGen/ARM64/fast-isel-fcmp.ll b/test/CodeGen/ARM64/fast-isel-fcmp.ll index cf71fab714..ab86132d45 100644 --- a/test/CodeGen/ARM64/fast-isel-fcmp.ll +++ b/test/CodeGen/ARM64/fast-isel-fcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin | FileCheck %s define zeroext i1 @fcmp_float1(float %a) nounwind ssp { entry: |