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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-05-10 14:09:52 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-05-10 14:09:52 +0000 |
| commit | 768ebcdf631baa1b18dc65a5983a237b307a99c2 (patch) | |
| tree | f15c5d03fd7d8385fa12f56be297f252b2ab785f | |
| parent | 51dab6e3945a6d06a713869967ced3a8f9fb6294 (diff) | |
| download | llvm-768ebcdf631baa1b18dc65a5983a237b307a99c2.tar.gz llvm-768ebcdf631baa1b18dc65a5983a237b307a99c2.tar.bz2 llvm-768ebcdf631baa1b18dc65a5983a237b307a99c2.tar.xz | |
DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)).
PR15948.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181597 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/X86/xor.ll | 11 |
2 files changed, 12 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 700ee12072..c54dffbb13 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3464,8 +3464,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && N0->getOperand(1) == N1) { SDValue X = N0->getOperand(0); - SDValue NotX = DAG.getNode(ISD::XOR, X.getDebugLoc(), VT, X, - DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); + SDValue NotX = DAG.getNOT(X.getDebugLoc(), X, VT); AddToWorkList(NotX.getNode()); return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NotX, N1); } diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index 2408bfe72c..574bb7817e 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -154,3 +154,14 @@ define i32 @test9(i32 %a) nounwind { ; X32: notl [[REG:%[a-z]+]] ; X32: andl {{.*}}[[REG:%[a-z]+]] } + +; PR15948 +define <4 x i32> @test10(<4 x i32> %a) nounwind { + %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096> + %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096> + ret <4 x i32> %2 +; X64: test10: +; X64: andnps +; X32: test10: +; X32: andnps +} |