split enum emission out from InstrInfoEmitter into it's own tblgen backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45640 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 89 insertions, 39 deletions

diff --git a/utils/TableGen/InstrEnumEmitter.cpp b/utils/TableGen/InstrEnumEmitter.cpp
new file mode 100644
index 0000000000..df07119944
--- /dev/null
+++ b/utils/TableGen/InstrEnumEmitter.cpp
@@ -0,0 +1,54 @@
+//===- InstrEnumEmitter.cpp - Generate Instruction Set Enums --------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend is responsible for emitting enums for each machine
+// instruction.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InstrEnumEmitter.h"
+#include "CodeGenTarget.h"
+#include "Record.h"
+using namespace llvm;
+
+// runEnums - Print out enum values for all of the instructions.
+void InstrEnumEmitter::run(std::ostream &OS) {
+  EmitSourceFileHeader("Target Instruction Enum Values", OS);
+  OS << "namespace llvm {\n\n";
+
+  CodeGenTarget Target;
+
+  // We must emit the PHI opcode first...
+  std::string Namespace;
+  for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 
+       E = Target.inst_end(); II != E; ++II) {
+    if (II->second.Namespace != "TargetInstrInfo") {
+      Namespace = II->second.Namespace;
+      break;
+    }
+  }
+  
+  if (Namespace.empty()) {
+    fprintf(stderr, "No instructions defined!\n");
+    exit(1);
+  }
+
+  std::vector<const CodeGenInstruction*> NumberedInstructions;
+  Target.getInstructionsByEnumValue(NumberedInstructions);
+
+  OS << "namespace " << Namespace << " {\n";
+  OS << "  enum {\n";
+  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+    OS << "    " << NumberedInstructions[i]->TheDef->getName()
+       << "\t= " << i << ",\n";
+  }
+  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+  OS << "  };\n}\n";
+  OS << "} // End llvm namespace \n";
+}
diff --git a/utils/TableGen/InstrEnumEmitter.h b/utils/TableGen/InstrEnumEmitter.h
new file mode 100644
index 0000000000..b39fef2d43
--- /dev/null
+++ b/utils/TableGen/InstrEnumEmitter.h
@@ -0,0 +1,33 @@
+//===- InstrEnumEmitter.h - Generate Instruction Set Enums ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend is responsible for emitting enums for each machine
+// instruction.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef INSTRENUM_EMITTER_H
+#define INSTRENUM_EMITTER_H
+
+#include "TableGenBackend.h"
+
+namespace llvm {
+
+class InstrEnumEmitter : public TableGenBackend {
+  RecordKeeper &Records;
+public:
+  InstrEnumEmitter(RecordKeeper &R) : Records(R) {}
+
+  // run - Output the instruction set description, returning true on failure.
+  void run(std::ostream &OS);
+};
+
+} // End llvm namespace
+
+#endif
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 004da9eaf1..10962041e7 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -19,42 +19,6 @@
 #include <iostream>
 using namespace llvm;
 
-// runEnums - Print out enum values for all of the instructions.
-void InstrInfoEmitter::runEnums(std::ostream &OS) {
-  EmitSourceFileHeader("Target Instruction Enum Values", OS);
-  OS << "namespace llvm {\n\n";
-
-  CodeGenTarget Target;
-
-  // We must emit the PHI opcode first...
-  std::string Namespace;
-  for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 
-       E = Target.inst_end(); II != E; ++II) {
-    if (II->second.Namespace != "TargetInstrInfo") {
-      Namespace = II->second.Namespace;
-      break;
-    }
-  }
-  
-  if (Namespace.empty()) {
-    std::cerr << "No instructions defined!\n";
-    exit(1);
-  }
-
-  std::vector<const CodeGenInstruction*> NumberedInstructions;
-  Target.getInstructionsByEnumValue(NumberedInstructions);
-
-  OS << "namespace " << Namespace << " {\n";
-  OS << "  enum {\n";
-  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
-    OS << "    " << NumberedInstructions[i]->TheDef->getName()
-       << "\t= " << i << ",\n";
-  }
-  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
-  OS << "  };\n}\n";
-  OS << "} // End llvm namespace \n";
-}
-
 void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
                                     unsigned Num, std::ostream &OS) const {
   OS << "static const unsigned ImplicitList" << Num << "[] = { ";
diff --git a/utils/TableGen/InstrInfoEmitter.h b/utils/TableGen/InstrInfoEmitter.h
index 27cf429fb9..fe40b5803d 100644
--- a/utils/TableGen/InstrInfoEmitter.h
+++ b/utils/TableGen/InstrInfoEmitter.h
@@ -37,8 +37,6 @@ public:
   // run - Output the instruction set description, returning true on failure.
   void run(std::ostream &OS);
 
-  // runEnums - Print out enum values for all of the instructions.
-  void runEnums(std::ostream &OS);
 private:
   void printDefList(const std::vector<Record*> &Uses, unsigned Num,
                     std::ostream &OS) const;
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 28e4a8a86f..b174ff8903 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -26,6 +26,7 @@
 #include "CodeEmitterGen.h"
 #include "RegisterInfoEmitter.h"
 #include "InstrInfoEmitter.h"
+#include "InstrEnumEmitter.h"
 #include "AsmWriterEmitter.h"
 #include "DAGISelEmitter.h"
 #include "SubtargetEmitter.h"
@@ -158,7 +159,7 @@ int main(int argc, char **argv) {
       break;
 
     case GenInstrEnums:
-      InstrInfoEmitter(Records).runEnums(*Out);
+      InstrEnumEmitter(Records).run(*Out);
       break;
     case GenInstrs:
       InstrInfoEmitter(Records).run(*Out);