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| author | Weiming Zhao <weimingz@codeaurora.org> | 2013-09-26 17:25:10 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2013-09-26 17:25:10 +0000 |
| commit | 82f36241c2484a72ba11b7ae5af3f485504a7b6e (patch) | |
| tree | afa41a035799d80042cae748eb96cc9a514d66ce | |
| parent | daf6b948b98b886f5f0fba130e91e01c9ca7c2f2 (diff) | |
| download | llvm-82f36241c2484a72ba11b7ae5af3f485504a7b6e.tar.gz llvm-82f36241c2484a72ba11b7ae5af3f485504a7b6e.tar.bz2 llvm-82f36241c2484a72ba11b7ae5af3f485504a7b6e.tar.xz | |
Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191441 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/prefetch-thumb.ll | 22 |
2 files changed, 29 insertions, 0 deletions
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 286eaa0946..82c57df74f 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -334,6 +334,7 @@ negativeOffsetOpcode(unsigned opcode) case ARM::t2STRi12: return ARM::t2STRi8; case ARM::t2STRBi12: return ARM::t2STRBi8; case ARM::t2STRHi12: return ARM::t2STRHi8; + case ARM::t2PLDi12: return ARM::t2PLDi8; case ARM::t2LDRi8: case ARM::t2LDRHi8: @@ -343,6 +344,7 @@ negativeOffsetOpcode(unsigned opcode) case ARM::t2STRi8: case ARM::t2STRBi8: case ARM::t2STRHi8: + case ARM::t2PLDi8: return opcode; default: @@ -364,6 +366,7 @@ positiveOffsetOpcode(unsigned opcode) case ARM::t2STRi8: return ARM::t2STRi12; case ARM::t2STRBi8: return ARM::t2STRBi12; case ARM::t2STRHi8: return ARM::t2STRHi12; + case ARM::t2PLDi8: return ARM::t2PLDi12; case ARM::t2LDRi12: case ARM::t2LDRHi12: @@ -373,6 +376,7 @@ positiveOffsetOpcode(unsigned opcode) case ARM::t2STRi12: case ARM::t2STRBi12: case ARM::t2STRHi12: + case ARM::t2PLDi12: return opcode; default: @@ -394,6 +398,7 @@ immediateOffsetOpcode(unsigned opcode) case ARM::t2STRs: return ARM::t2STRi12; case ARM::t2STRBs: return ARM::t2STRBi12; case ARM::t2STRHs: return ARM::t2STRHi12; + case ARM::t2PLDs: return ARM::t2PLDi12; case ARM::t2LDRi12: case ARM::t2LDRHi12: @@ -403,6 +408,7 @@ immediateOffsetOpcode(unsigned opcode) case ARM::t2STRi12: case ARM::t2STRBi12: case ARM::t2STRHi12: + case ARM::t2PLDi12: case ARM::t2LDRi8: case ARM::t2LDRHi8: case ARM::t2LDRBi8: @@ -411,6 +417,7 @@ immediateOffsetOpcode(unsigned opcode) case ARM::t2STRi8: case ARM::t2STRBi8: case ARM::t2STRHi8: + case ARM::t2PLDi8: return opcode; default: diff --git a/test/CodeGen/ARM/prefetch-thumb.ll b/test/CodeGen/ARM/prefetch-thumb.ll new file mode 100644 index 0000000000..e6f6ae8d18 --- /dev/null +++ b/test/CodeGen/ARM/prefetch-thumb.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 +; TODO: This test case will be merged back into prefetch.ll when ARM mode issue is solved. + +declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind + +define void @t6() { +entry: +;ARM: t6: +;ARM: pld [sp] +;ARM: pld [sp, #50] + +;THUMB2: t6: +;THUMB2: pld [sp] +;THUMB2: pld [sp, #50] + +%red = alloca [100 x i8], align 1 +%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0 +%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50 +call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) +call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) +ret void +} |