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authorAlkis Evlogimenos <alkis@evlogimenos.com>2004-04-02 07:11:10 +0000
committerAlkis Evlogimenos <alkis@evlogimenos.com>2004-04-02 07:11:10 +0000
commit8b28b6d187282367e1d1c8f9a155a10bcfef52de (patch)
tree978aa589e83eb6ae98deb837b22e0f4c1acc85e9
parent02bb481881fe6aaa876f9bf79f38f40f56a35a01 (diff)
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Add more ADC and SBB variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12607 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat
-rw-r--r--lib/Target/X86/PeepholeOptimizer.cpp12
-rw-r--r--lib/Target/X86/X86InstrInfo.td21
-rw-r--r--lib/Target/X86/X86PeepholeOpt.cpp12
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp2
4 files changed, 32 insertions, 15 deletions
diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index bc29472621..a1ef1c763e 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -123,8 +123,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
return false;
#endif
- case X86::ADD16ri: case X86::ADD32ri:
- case X86::SUB16ri: case X86::SUB32ri:
+ case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
+ case X86::SUB16ri: case X86::SUB32ri: case X86::SBB32ri:
case X86::AND16ri: case X86::AND32ri:
case X86::OR16ri: case X86::OR32ri:
case X86::XOR16ri: case X86::XOR32ri:
@@ -138,8 +138,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
default: assert(0 && "Unknown opcode value!");
case X86::ADD16ri: Opcode = X86::ADD16ri8; break;
case X86::ADD32ri: Opcode = X86::ADD32ri8; break;
+ case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
+ case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
case X86::AND16ri: Opcode = X86::AND16ri8; break;
case X86::AND32ri: Opcode = X86::AND32ri8; break;
case X86::OR16ri: Opcode = X86::OR16ri8; break;
@@ -156,8 +158,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
}
return false;
- case X86::ADD16mi: case X86::ADD32mi:
- case X86::SUB16mi: case X86::SUB32mi:
+ case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
+ case X86::SUB16mi: case X86::SUB32mi: case X86::SBB32mi:
case X86::AND16mi: case X86::AND32mi:
case X86::OR16mi: case X86::OR32mi:
case X86::XOR16mi: case X86::XOR32mi:
@@ -171,8 +173,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
default: assert(0 && "Unknown opcode value!");
case X86::ADD16mi: Opcode = X86::ADD16mi8; break;
case X86::ADD32mi: Opcode = X86::ADD32mi8; break;
+ case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
+ case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
case X86::AND16mi: Opcode = X86::AND16mi8; break;
case X86::AND32mi: Opcode = X86::AND32mi8; break;
case X86::OR16mi: Opcode = X86::OR16mi8; break;
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index d32dd3e12b..201a803d41 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -531,10 +531,13 @@ def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >;
def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
-def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
-def ADC32rm : Im32 <"adc", 0x11, MRMSrcMem >; // R32 += [mem32]+Carry
-def ADC32mr : Im32 <"adc", 0x13, MRMDestMem>; // [mem32] += R32+Carry
-
+def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
+def ADC32rm : Im32 <"adc", 0x11, MRMSrcMem >; // R32 += [mem32]+Carry
+def ADC32mr : Im32 <"adc", 0x13, MRMDestMem>; // [mem32] += R32+Carry
+def ADC32ri : Ii32 <"adc", 0x81, MRM2r >; // R32 += I32+Carry
+def ADC32ri8 : Ii8 <"adc", 0x83, MRM2r >; // R32 += I8+Carry
+def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry
+def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32[ += I8+Carry
def SUB8rr : I <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
@@ -558,9 +561,13 @@ def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >;
def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
-def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Borrow
-def SBB32rm : Im32 <"sbb", 0x19, MRMSrcMem >; // R32 -= [mem32]+Borrow
-def SBB32mr : Im32 <"sbb", 0x1B, MRMDestMem>; // [mem32] -= R32+Borrow
+def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Borrow
+def SBB32rm : Im32 <"sbb", 0x19, MRMSrcMem >; // R32 -= [mem32]+Borrow
+def SBB32mr : Im32 <"sbb", 0x1B, MRMDestMem>; // [mem32] -= R32+Borrow
+def SBB32ri : Ii32 <"adc", 0x81, MRM3r >; // R32 -= I32+Borrow
+def SBB32ri8 : Ii8 <"adc", 0x83, MRM3r >; // R32 -= I8+Borrow
+def SBB32mi : Im32i32<"adc", 0x81, MRM3m >; // [mem32] -= I32+Borrow
+def SBB32mi8 : Im32i8 <"adc", 0x83, MRM3m >; // [mem32[ -= I8+Borrow
def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index bc29472621..a1ef1c763e 100644
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -123,8 +123,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
return false;
#endif
- case X86::ADD16ri: case X86::ADD32ri:
- case X86::SUB16ri: case X86::SUB32ri:
+ case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
+ case X86::SUB16ri: case X86::SUB32ri: case X86::SBB32ri:
case X86::AND16ri: case X86::AND32ri:
case X86::OR16ri: case X86::OR32ri:
case X86::XOR16ri: case X86::XOR32ri:
@@ -138,8 +138,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
default: assert(0 && "Unknown opcode value!");
case X86::ADD16ri: Opcode = X86::ADD16ri8; break;
case X86::ADD32ri: Opcode = X86::ADD32ri8; break;
+ case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
+ case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
case X86::AND16ri: Opcode = X86::AND16ri8; break;
case X86::AND32ri: Opcode = X86::AND32ri8; break;
case X86::OR16ri: Opcode = X86::OR16ri8; break;
@@ -156,8 +158,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
}
return false;
- case X86::ADD16mi: case X86::ADD32mi:
- case X86::SUB16mi: case X86::SUB32mi:
+ case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
+ case X86::SUB16mi: case X86::SUB32mi: case X86::SBB32mi:
case X86::AND16mi: case X86::AND32mi:
case X86::OR16mi: case X86::OR32mi:
case X86::XOR16mi: case X86::XOR32mi:
@@ -171,8 +173,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
default: assert(0 && "Unknown opcode value!");
case X86::ADD16mi: Opcode = X86::ADD16mi8; break;
case X86::ADD32mi: Opcode = X86::ADD32mi8; break;
+ case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
+ case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
case X86::AND16mi: Opcode = X86::AND16mi8; break;
case X86::AND32mi: Opcode = X86::AND32mi8; break;
case X86::OR16mi: Opcode = X86::OR16mi8; break;
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 556bfd10b3..2d0c871f98 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -176,6 +176,7 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
+ case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
@@ -183,6 +184,7 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
+ case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 04:44:18 +0000