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| author | Richard Osborne <richard@xmos.com> | 2011-05-31 16:24:49 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-05-31 16:24:49 +0000 |
| commit | 9497466190a46ba06bf856302b1c81f1c4b5c951 (patch) | |
| tree | 19e5385b7600894f5fa22e3bc8458a5ea44f645d | |
| parent | 7736c37c142f05f4ba53c52973658bf9abc6f4cc (diff) | |
| download | llvm-9497466190a46ba06bf856302b1c81f1c4b5c951.tar.gz llvm-9497466190a46ba06bf856302b1c81f1c4b5c951.tar.bz2 llvm-9497466190a46ba06bf856302b1c81f1c4b5c951.tar.xz | |
Add XCore intrinsic for crc8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132340 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/IntrinsicsXCore.td | 3 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreISelDAGToDAG.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 6 | ||||
| -rw-r--r-- | test/CodeGen/XCore/misc-intrinsics.ll | 10 |
4 files changed, 29 insertions, 0 deletions
diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td index 951f7dd700..bab79b2bf8 100644 --- a/include/llvm/IntrinsicsXCore.td +++ b/include/llvm/IntrinsicsXCore.td @@ -11,6 +11,9 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". // Miscellaneous instructions. def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>; + def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], + [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 6bec9f9194..a8dd8479d4 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -205,6 +205,16 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) { return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, Ops, 4); } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_crc8: + SDValue Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, + Ops, 3); + } + break; + } case ISD::BRIND: if (SDNode *ResNode = SelectBRIND(N)) return ResNode; diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 1647db5d78..492596d1f3 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -504,6 +504,12 @@ def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), []>; } +let Constraints = "$src1 = $dst1" in +def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "crc8 $dst1, $dst2, $src2, $src3", + []>; + // Five operand long def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll index 0c684886ee..f504a2ed72 100644 --- a/test/CodeGen/XCore/misc-intrinsics.ll +++ b/test/CodeGen/XCore/misc-intrinsics.ll @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=xcore | FileCheck %s +%0 = type { i32, i32 } + declare i32 @llvm.xcore.bitrev(i32) declare i32 @llvm.xcore.crc32(i32, i32, i32) +declare %0 @llvm.xcore.crc8(i32, i32, i32) define i32 @bitrev(i32 %val) { ; CHECK: bitrev: @@ -15,3 +18,10 @@ define i32 @crc32(i32 %crc, i32 %data, i32 %poly) { %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly) ret i32 %result } + +define %0 @crc8(i32 %crc, i32 %data, i32 %poly) { +; CHECK: crc8: +; CHECK: crc8 r0, r1, r1, r2 + %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) + ret %0 %result +} |