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author | Rafael Espindola <rafael.espindola@gmail.com> | 2013-12-11 01:07:43 +0000 |
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committer | Rafael Espindola <rafael.espindola@gmail.com> | 2013-12-11 01:07:43 +0000 |
commit | a3b00b504ecb389c950178902a10ab2cff91ba58 (patch) | |
tree | de205b3158527427b0766568ca6294aa1ef3f702 | |
parent | 0d87d72fa7d371950a17a18716984640373b09e7 (diff) | |
download | llvm-a3b00b504ecb389c950178902a10ab2cff91ba58.tar.gz llvm-a3b00b504ecb389c950178902a10ab2cff91ba58.tar.bz2 llvm-a3b00b504ecb389c950178902a10ab2cff91ba58.tar.xz |
Move Sparc's getDataLayout out of line and add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196990 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Sparc/SparcSubtarget.h | 9 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcTargetMachine.cpp | 25 |
2 files changed, 24 insertions, 10 deletions
diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h index 0f81cc960f..012aca7d92 100644 --- a/lib/Target/Sparc/SparcSubtarget.h +++ b/lib/Target/Sparc/SparcSubtarget.h @@ -45,15 +45,6 @@ public: void ParseSubtargetFeatures(StringRef CPU, StringRef FS); bool is64Bit() const { return Is64Bit; } - std::string getDataLayout() const { - const char *p; - if (is64Bit()) { - p = "E-p:64:64:64-i64:64:64-f64:64:64-f128:128:128-n32:64"; - } else { - p = "E-p:32:32:32-i64:64:64-f64:64:64-f128:64:64-n32"; - } - return std::string(p); - } /// The 64-bit ABI uses biased stack and frame pointers, so the stack frame /// of the current function is the area from [%sp+BIAS] to [%fp+BIAS]. diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 0f936747cf..654b625500 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -23,6 +23,29 @@ extern "C" void LLVMInitializeSparcTarget() { RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); } +static std::string computeDataLayout(const SparcSubtarget &ST) { + // Sparc is big endian. + std::string Ret = "E"; + + // V9 has 64 bit pointers, others have 32bit pointers. + if (ST.is64Bit()) + Ret += "-p:64:64:64"; + else + Ret += "-p:32:32:32"; + + // Alignments for 64 bit integers and doubles. + Ret += "-i64:64:64-f64:64:64"; + + // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. + // On SparcV9 registers can hold 64 or 32 bits, on others only 32. + if (ST.is64Bit()) + Ret += "-f128:128:128-n32:64"; + else + Ret += "-f128:64:64-n32"; + + return Ret; +} + /// SparcTargetMachine ctor - Create an ILP32 architecture model /// SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, @@ -33,7 +56,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, bool is64bit) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), Subtarget(TT, CPU, FS, is64bit), - DL(Subtarget.getDataLayout()), + DL(computeDataLayout(Subtarget)), InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget) { |