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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:20 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:20 +0000 |
| commit | a6a39ced095c2f453624ce62c4aead25db41a18f (patch) | |
| tree | b7ae0e904a814233601cf7c343a860bbf5f64809 | |
| parent | 30d84d8dfa0433088d541c66b92af0da3855bc9c (diff) | |
| download | llvm-a6a39ced095c2f453624ce62c4aead25db41a18f.tar.gz llvm-a6a39ced095c2f453624ce62c4aead25db41a18f.tar.bz2 llvm-a6a39ced095c2f453624ce62c4aead25db41a18f.tar.xz | |
R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions
The SIInsertWaits pass was overwriting the first operand (gds bit) of
DS_WRITE_B32 with the second operand (value to write). This meant that
any time the value to write was stored in an odd number VGPR, the gds
bit would be set causing the instruction to write to GDS instead of LDS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188522 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInsertWaits.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 6 | ||||
| -rw-r--r-- | test/CodeGen/R600/local-memory.ll | 4 |
4 files changed, 10 insertions, 12 deletions
diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp index ba202e3cbf..c477be5a89 100644 --- a/lib/Target/R600/SIInsertWaits.cpp +++ b/lib/Target/R600/SIInsertWaits.cpp @@ -134,9 +134,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { // LGKM may uses larger values if (TSFlags & SIInstrFlags::LGKM_CNT) { - MachineOperand &Op = MI.getOperand(0); - if (!Op.isReg()) - Op = MI.getOperand(1); + const MachineOperand &Op = MI.getOperand(0); assert(Op.isReg() && "First LGKM operand must be a register!"); unsigned Reg = Op.getReg(); diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index ecc471817e..1965ba0d34 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -342,8 +342,8 @@ class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < op, (outs regClass:$vdst), - (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, - i8imm:$offset0, i8imm:$offset1), + (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, + i8imm:$offset0, i8imm:$offset1, i1imm:$gds), asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]", []> { let mayLoad = 1; @@ -353,8 +353,8 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < op, (outs), - (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, - i8imm:$offset0, i8imm:$offset1), + (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1, + i8imm:$offset0, i8imm:$offset1, i1imm:$gds), asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]", []> { let mayStore = 1; diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 4eb3566c01..9856fa68b4 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1745,13 +1745,13 @@ def : Pat < def : Pat < (local_load i64:$src0), - (i32 (DS_READ_B32 0, (EXTRACT_SUBREG $src0, sub0), - (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0)) + (i32 (DS_READ_B32 (EXTRACT_SUBREG $src0, sub0), + (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0, 0)) >; def : Pat < (local_store i32:$src1, i64:$src0), - (DS_WRITE_B32 0, (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0) + (DS_WRITE_B32 (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0, 0) >; /********** ================== **********/ diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll index 5458fb9057..ca322ab82a 100644 --- a/test/CodeGen/R600/local-memory.ll +++ b/test/CodeGen/R600/local-memory.ll @@ -13,7 +13,7 @@ ; SI-CHECK-NEXT: .long 32768 ; EG-CHECK: LDS_WRITE -; SI-CHECK: DS_WRITE_B32 +; SI-CHECK: DS_WRITE_B32 0 ; GROUP_BARRIER must be the last instruction in a clause ; EG-CHECK: GROUP_BARRIER @@ -21,7 +21,7 @@ ; SI-CHECK: S_BARRIER ; EG-CHECK: LDS_READ_RET -; SI-CHECK: DS_READ_B32 +; SI-CHECK: DS_READ_B32 VGPR{{[0-9]}}, 0 define void @local_memory(i32 addrspace(1)* %out) { entry: |