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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-08 19:38:04 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-05-08 19:38:04 +0000 |
| commit | b637b9f89e88e8c1ffe147634c1b2b297fb6edeb (patch) | |
| tree | 10c7697976315eed932aa508332138285d060d04 | |
| parent | 146f336272f442e8342ef9bbfa5f5937c4bb8d65 (diff) | |
| download | llvm-b637b9f89e88e8c1ffe147634c1b2b297fb6edeb.tar.gz llvm-b637b9f89e88e8c1ffe147634c1b2b297fb6edeb.tar.bz2 llvm-b637b9f89e88e8c1ffe147634c1b2b297fb6edeb.tar.xz | |
[mips] Add instruction selection pattern for (seteq $LHS, 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181459 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/setcc-se.ll | 11 |
2 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 86ec72982b..3d319373fe 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1263,6 +1263,8 @@ defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; // setcc patterns multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, Instruction SLTuOp, Register ZEROReg> { + def : MipsPat<(seteq RC:$lhs, 0), + (SLTiuOp RC:$lhs, 1)>; def : MipsPat<(seteq RC:$lhs, RC:$rhs), (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; def : MipsPat<(setne RC:$lhs, RC:$rhs), diff --git a/test/CodeGen/Mips/setcc-se.ll b/test/CodeGen/Mips/setcc-se.ll new file mode 100644 index 0000000000..6679536164 --- /dev/null +++ b/test/CodeGen/Mips/setcc-se.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +; CHECK: seteq0: +; CHECK: sltiu ${{[0-9]+}}, $4, 1 + +define i32 @seteq0(i32 %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} |