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author | Andrew Trick <atrick@apple.com> | 2013-09-26 05:53:35 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-09-26 05:53:35 +0000 |
commit | b6ac11cd03e9dd97b45dc97787171f942ef8e344 (patch) | |
tree | c3a5445d795ffac70245f791c111588b6d3703ee | |
parent | 7394a7c0c27d498fe7ff0760eeefdb83bb54a795 (diff) | |
download | llvm-b6ac11cd03e9dd97b45dc97787171f942ef8e344.tar.gz llvm-b6ac11cd03e9dd97b45dc97787171f942ef8e344.tar.bz2 llvm-b6ac11cd03e9dd97b45dc97787171f942ef8e344.tar.xz |
Added temp flag -misched-bench for staging in default changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 3 | ||||
-rw-r--r-- | lib/CodeGen/Passes.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/RegisterCoalescer.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 | ||||
-rw-r--r-- | lib/Target/TargetSubtargetInfo.cpp | 17 |
5 files changed, 22 insertions, 4 deletions
diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index 37365b2a9c..1b2e06acc2 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -56,6 +56,9 @@ public: return 0; } + /// \brief Temporary API to test migration to MI scheduler. + bool useMachineScheduler() const; + /// \brief True if the subtarget should run MachineScheduler after aggressive /// coalescing. /// diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp index c0861c58fd..84eb8b876f 100644 --- a/lib/CodeGen/Passes.cpp +++ b/lib/CodeGen/Passes.cpp @@ -236,7 +236,7 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) // Temporarily disable experimental passes. const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>(); - if (!ST.enableMachineScheduler()) + if (!ST.useMachineScheduler()) disablePass(&MachineSchedulerID); } diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index c776dd3122..791f1baf63 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -2199,7 +2199,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) { const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>(); if (EnableGlobalCopies == cl::BOU_UNSET) - JoinGlobalCopies = ST.enableMachineScheduler(); + JoinGlobalCopies = ST.useMachineScheduler(); else JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 8369fd3a97..6d097a68f8 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -230,7 +230,7 @@ namespace llvm { const TargetLowering *TLI = IS->getTargetLowering(); const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); - if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || + if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() || TLI->getSchedulingPreference() == Sched::Source) return createSourceListDAGScheduler(IS, OptLevel); if (TLI->getSchedulingPreference() == Sched::RegPressure) diff --git a/lib/Target/TargetSubtargetInfo.cpp b/lib/Target/TargetSubtargetInfo.cpp index f624c321ab..10e8db5925 100644 --- a/lib/Target/TargetSubtargetInfo.cpp +++ b/lib/Target/TargetSubtargetInfo.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/ADT/SmallVector.h" using namespace llvm; @@ -22,6 +23,21 @@ TargetSubtargetInfo::TargetSubtargetInfo() {} TargetSubtargetInfo::~TargetSubtargetInfo() {} +// Temporary option to compare overall performance change when moving from the +// SD scheduler to the MachineScheduler pass pipeline. It should be removed +// before 3.4. The normal way to enable/disable the MachineScheduling pass +// itself is by using -enable-misched. For targets that already use MI sched +// (via MySubTarget::enableMachineScheduler()) -misched-bench=false negates the +// subtarget hook. +static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden, + cl::desc("Migrate from the target's default SD scheduler to MI scheduler")); + +bool TargetSubtargetInfo::useMachineScheduler() const { + if (BenchMachineSched.getNumOccurrences()) + return BenchMachineSched; + return enableMachineScheduler(); +} + bool TargetSubtargetInfo::enableMachineScheduler() const { return false; } @@ -38,4 +54,3 @@ bool TargetSubtargetInfo::enablePostRAScheduler( bool TargetSubtargetInfo::useAA() const { return false; } - |