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authorHal Finkel <hfinkel@anl.gov>2013-11-30 20:41:13 +0000
committerHal Finkel <hfinkel@anl.gov>2013-11-30 20:41:13 +0000
commitbc0bdb26da10037e182d83707aeb51b49ae35d8a (patch)
tree265e2fed2c383433b456d57a11a2fd8348d39359
parent6e1de2e63ee831e01b6e7eaa123e1e0e270bac76 (diff)
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Split some PPC itinerary classes
In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195980 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat
-rw-r--r--lib/Target/PowerPC/PPCInstr64Bit.td16
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td18
-rw-r--r--lib/Target/PowerPC/PPCSchedule.td31
-rw-r--r--lib/Target/PowerPC/PPCSchedule440.td28
-rw-r--r--lib/Target/PowerPC/PPCScheduleA2.td16
-rw-r--r--lib/Target/PowerPC/PPCScheduleE500mc.td22
-rw-r--r--lib/Target/PowerPC/PPCScheduleE5500.td35
-rw-r--r--lib/Target/PowerPC/PPCScheduleG3.td3
-rw-r--r--lib/Target/PowerPC/PPCScheduleG4.td3
-rw-r--r--lib/Target/PowerPC/PPCScheduleG4Plus.td4
-rw-r--r--lib/Target/PowerPC/PPCScheduleG5.td9
11 files changed, 154 insertions, 31 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 038c1c1156..139be7e7d4 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -276,7 +276,7 @@ def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
- "mfocrf $rT, $FXM", IIC_SprMFCR>,
+ "mfocrf $rT, $FXM", IIC_SprMFCRF>,
PPC970_DGroup_First, PPC970_Unit_CRU;
def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
@@ -665,12 +665,12 @@ def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
let Interpretation64Bit = 1 in
def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lhaux $rD, $addr", IIC_LdStLHAU,
+ "lhaux $rD, $addr", IIC_LdStLHAUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lwaux $rD, $addr", IIC_LdStLHAU,
+ "lwaux $rD, $addr", IIC_LdStLHAUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64;
}
@@ -717,17 +717,17 @@ def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$add
def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lbzux $rD, $addr", IIC_LdStLoadUpd,
+ "lbzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lhzux $rD, $addr", IIC_LdStLoadUpd,
+ "lhzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lwzux $rD, $addr", IIC_LdStLoadUpd,
+ "lwzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
}
@@ -782,7 +782,7 @@ def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:
def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "ldux $rD, $addr", IIC_LdStLDU,
+ "ldux $rD, $addr", IIC_LdStLDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64;
}
@@ -936,7 +936,7 @@ def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$d
} // Interpretation64Bit
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
- "stdux $rS, $dst", IIC_LdStSTDU, []>,
+ "stdux $rS, $dst", IIC_LdStSTDUX, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked, isPPC64;
}
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 935b2e35fc..8754b40e09 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1330,37 +1330,37 @@ def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr
// Indexed (r+r) Loads with Update (preinc).
def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lbzux $rD, $addr", IIC_LdStLoadUpd,
+ "lbzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lhaux $rD, $addr", IIC_LdStLHAU,
+ "lhaux $rD, $addr", IIC_LdStLHAUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lhzux $rD, $addr", IIC_LdStLoadUpd,
+ "lhzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lwzux $rD, $addr", IIC_LdStLoadUpd,
+ "lwzux $rD, $addr", IIC_LdStLoadUpdX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lfsux $rD, $addr", IIC_LdStLFDU,
+ "lfsux $rD, $addr", IIC_LdStLFDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr),
- "lfdux $rD, $addr", IIC_LdStLFDU,
+ "lfdux $rD, $addr", IIC_LdStLFDUX,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">;
}
@@ -1740,10 +1740,10 @@ let Uses = [RM] in {
[(set f32:$frD, (ffloor f32:$frB))]>;
defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
- "fsqrt", "$frD, $frB", IIC_FPSqrt,
+ "fsqrt", "$frD, $frB", IIC_FPSqrtD,
[(set f64:$frD, (fsqrt f64:$frB))]>;
defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
- "fsqrts", "$frD, $frB", IIC_FPSqrt,
+ "fsqrts", "$frD, $frB", IIC_FPSqrtS,
[(set f32:$frD, (fsqrt f32:$frB))]>;
}
}
@@ -1948,7 +1948,7 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
- "mfocrf $rT, $FXM", IIC_SprMFCR>,
+ "mfocrf $rT, $FXM", IIC_SprMFCRF>,
PPC970_DGroup_First, PPC970_Unit_CRU;
def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td
index 452db1581d..ce048f9d22 100644
--- a/lib/Target/PowerPC/PPCSchedule.td
+++ b/lib/Target/PowerPC/PPCSchedule.td
@@ -39,17 +39,21 @@ def IIC_LdStDCBF : InstrItinClass;
def IIC_LdStDCBI : InstrItinClass;
def IIC_LdStLoad : InstrItinClass;
def IIC_LdStLoadUpd : InstrItinClass;
+def IIC_LdStLoadUpdX : InstrItinClass;
def IIC_LdStStore : InstrItinClass;
def IIC_LdStStoreUpd : InstrItinClass;
def IIC_LdStDSS : InstrItinClass;
def IIC_LdStICBI : InstrItinClass;
def IIC_LdStLD : InstrItinClass;
def IIC_LdStLDU : InstrItinClass;
+def IIC_LdStLDUX : InstrItinClass;
def IIC_LdStLDARX : InstrItinClass;
def IIC_LdStLFD : InstrItinClass;
def IIC_LdStLFDU : InstrItinClass;
+def IIC_LdStLFDUX : InstrItinClass;
def IIC_LdStLHA : InstrItinClass;
def IIC_LdStLHAU : InstrItinClass;
+def IIC_LdStLHAUX : InstrItinClass;
def IIC_LdStLMW : InstrItinClass;
def IIC_LdStLVecX : InstrItinClass;
def IIC_LdStLWA : InstrItinClass;
@@ -59,6 +63,7 @@ def IIC_LdStSLBIE : InstrItinClass;
def IIC_LdStSTD : InstrItinClass;
def IIC_LdStSTDCX : InstrItinClass;
def IIC_LdStSTDU : InstrItinClass;
+def IIC_LdStSTDUX : InstrItinClass;
def IIC_LdStSTFD : InstrItinClass;
def IIC_LdStSTFDU : InstrItinClass;
def IIC_LdStSTVEBX : InstrItinClass;
@@ -70,6 +75,7 @@ def IIC_SprMTMSR : InstrItinClass;
def IIC_SprMTSR : InstrItinClass;
def IIC_SprTLBSYNC : InstrItinClass;
def IIC_SprMFCR : InstrItinClass;
+def IIC_SprMFCRF : InstrItinClass;
def IIC_SprMFMSR : InstrItinClass;
def IIC_SprMFSPR : InstrItinClass;
def IIC_SprMFTB : InstrItinClass;
@@ -84,7 +90,8 @@ def IIC_FPDivD : InstrItinClass;
def IIC_FPDivS : InstrItinClass;
def IIC_FPFused : InstrItinClass;
def IIC_FPRes : InstrItinClass;
-def IIC_FPSqrt : InstrItinClass;
+def IIC_FPSqrtD : InstrItinClass;
+def IIC_FPSqrtS : InstrItinClass;
def IIC_VecGeneral : InstrItinClass;
def IIC_VecFP : InstrItinClass;
def IIC_VecFPCompare : InstrItinClass;
@@ -202,37 +209,37 @@ include "PPCScheduleE5500.td"
// frsp IIC_FPGeneral
// frsqrte IIC_FPGeneral
// fsel IIC_FPGeneral
-// fsqrt IIC_FPSqrt
-// fsqrts IIC_FPSqrt
+// fsqrt IIC_FPSqrtD
+// fsqrts IIC_FPSqrtS
// fsub IIC_FPAddSub
// fsubs IIC_FPGeneral
// icbi IIC_LdStICBI
// isync IIC_SprISYNC
// lbz IIC_LdStLoad
// lbzu IIC_LdStLoadUpd
-// lbzux IIC_LdStLoadUpd
+// lbzux IIC_LdStLoadUpdX
// lbzx IIC_LdStLoad
// ld IIC_LdStLD
// ldarx IIC_LdStLDARX
// ldu IIC_LdStLDU
-// ldux IIC_LdStLDU
+// ldux IIC_LdStLDUX
// ldx IIC_LdStLD
// lfd IIC_LdStLFD
// lfdu IIC_LdStLFDU
-// lfdux IIC_LdStLFDU
+// lfdux IIC_LdStLFDUX
// lfdx IIC_LdStLFD
// lfs IIC_LdStLFD
// lfsu IIC_LdStLFDU
-// lfsux IIC_LdStLFDU
+// lfsux IIC_LdStLFDUX
// lfsx IIC_LdStLFD
// lha IIC_LdStLHA
// lhau IIC_LdStLHAU
-// lhaux IIC_LdStLHAU
+// lhaux IIC_LdStLHAUX
// lhax IIC_LdStLHA
// lhbrx IIC_LdStLoad
// lhz IIC_LdStLoad
// lhzu IIC_LdStLoadUpd
-// lhzux IIC_LdStLoadUpd
+// lhzux IIC_LdStLoadUpdX
// lhzx IIC_LdStLoad
// lmw IIC_LdStLMW
// lswi IIC_LdStLMW
@@ -246,12 +253,12 @@ include "PPCScheduleE5500.td"
// lvxl IIC_LdStLVecX
// lwa IIC_LdStLWA
// lwarx IIC_LdStLWARX
-// lwaux IIC_LdStLHAU
+// lwaux IIC_LdStLHAUX
// lwax IIC_LdStLHA
// lwbrx IIC_LdStLoad
// lwz IIC_LdStLoad
// lwzu IIC_LdStLoadUpd
-// lwzux IIC_LdStLoadUpd
+// lwzux IIC_LdStLoadUpdX
// lwzx IIC_LdStLoad
// mcrf IIC_BrMCR
// mcrfs IIC_FPGeneral
@@ -320,7 +327,7 @@ include "PPCScheduleE5500.td"
// std IIC_LdStSTD
// stdcx. IIC_LdStSTDCX
// stdu IIC_LdStSTDU
-// stdux IIC_LdStSTDU
+// stdux IIC_LdStSTDUX
// stdx IIC_LdStSTD
// stfd IIC_LdStSTFD
// stfdu IIC_LdStSTFDU
diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td
index 780fa4779b..218fed248a 100644
--- a/lib/Target/PowerPC/PPCSchedule440.td
+++ b/lib/Target/PowerPC/PPCSchedule440.td
@@ -258,6 +258,13 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [P440_LWB]>],
[5, 2, 1, 1],
[P440_GPR_Bypass, P440_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
+ InstrStage<1, [P440_LRACC]>,
+ InstrStage<1, [P440_AGEN]>,
+ InstrStage<1, [P440_CRD]>,
+ InstrStage<2, [P440_LWB]>],
+ [5, 2, 1, 1],
+ [P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
@@ -307,6 +314,13 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [P440_LWB]>],
[5, 2, 1, 1],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+ InstrStage<1, [P440_LRACC]>,
+ InstrStage<1, [P440_AGEN]>,
+ InstrStage<1, [P440_CRD]>,
+ InstrStage<1, [P440_LWB]>],
+ [5, 2, 1, 1],
+ [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
@@ -321,6 +335,13 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [P440_LWB]>],
[4, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+ InstrStage<1, [P440_LRACC]>,
+ InstrStage<1, [P440_AGEN]>,
+ InstrStage<1, [P440_CRD]>,
+ InstrStage<1, [P440_LWB]>],
+ [4, 1, 1],
+ [NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
@@ -351,6 +372,13 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [P440_LWB]>],
[2, 1, 1, 1],
[NoBypass, P440_GPR_Bypass]>,
+ InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+ InstrStage<1, [P440_LRACC]>,
+ InstrStage<1, [P440_AGEN]>,
+ InstrStage<1, [P440_CRD]>,
+ InstrStage<2, [P440_LWB]>],
+ [2, 1, 1, 1],
+ [NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
InstrStage<1, [P440_IRACC], 0>,
InstrStage<4, [P440_LWARX_Hold], 0>,
diff --git a/lib/Target/PowerPC/PPCScheduleA2.td b/lib/Target/PowerPC/PPCScheduleA2.td
index bd95924be8..14476963ba 100644
--- a/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/lib/Target/PowerPC/PPCScheduleA2.td
@@ -71,8 +71,12 @@ def PPCA2Itineraries : ProcessorItineraries<
[6, 0, 0]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
[6, 8, 0, 0]>,
+ InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
+ [6, 8, 0, 0]>,
InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
[6, 0, 0]>,
+ InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>],
+ [6, 0, 0]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
[0, 0, 0]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
@@ -87,16 +91,22 @@ def PPCA2Itineraries : ProcessorItineraries<
[7, 0, 0]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
[7, 9, 0, 0]>,
+ InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [A2_XU]>],
+ [7, 9, 0, 0]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
[6, 0, 0]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
[6, 8, 0, 0]>,
+ InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [A2_XU]>],
+ [6, 8, 0, 0]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
[82, 0, 0]>, // L2 latency
InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
[0, 0, 0]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
[2, 0, 0, 0]>,
+ InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>],
+ [2, 0, 0, 0]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
[82, 0, 0]>, // L2 latency
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
@@ -109,6 +119,8 @@ def PPCA2Itineraries : ProcessorItineraries<
[16, 0]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
[6, 0]>,
+ InstrItinData<IIC_SprMFCRF, [InstrStage<1, [A2_XU]>],
+ [1, 0]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
[4, 0]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
@@ -131,8 +143,10 @@ def PPCA2Itineraries : ProcessorItineraries<
[72, 0, 0]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
[59, 0, 0]>,
- InstrItinData<IIC_FPSqrt, [InstrStage<1, [A2_FU]>],
+ InstrItinData<IIC_FPSqrtD, [InstrStage<1, [A2_FU]>],
[69, 0, 0]>,
+ InstrItinData<IIC_FPSqrtS, [InstrStage<1, [A2_FU]>],
+ [65, 0, 0]>,
InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
[6, 0, 0, 0]>,
InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
diff --git a/lib/Target/PowerPC/PPCScheduleE500mc.td b/lib/Target/PowerPC/PPCScheduleE500mc.td
index 906c685d54..dab89e3db3 100644
--- a/lib/Target/PowerPC/PPCScheduleE500mc.td
+++ b/lib/Target/PowerPC/PPCScheduleE500mc.td
@@ -141,6 +141,12 @@ def PPCE500mcItineraries : ProcessorItineraries<
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500_GPR_Bypass, E500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
@@ -179,6 +185,13 @@ def PPCE500mcItineraries : ProcessorItineraries<
[E500_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_LSU_0]>],
+ [7, 1, 1], // Latency = 4
+ [E500_FPR_Bypass,
+ E500_GPR_Bypass, E500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
@@ -188,6 +201,11 @@ def PPCE500mcItineraries : ProcessorItineraries<
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[7, 1], // Latency = r+3
@@ -221,6 +239,10 @@ def PPCE500mcItineraries : ProcessorItineraries<
InstrStage<5, [E500_SFX0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
+ InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<5, [E500_SFX0]>],
+ [8, 1],
+ [E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
diff --git a/lib/Target/PowerPC/PPCScheduleE5500.td b/lib/Target/PowerPC/PPCScheduleE5500.td
index 0de04fb2be..de097d9d8c 100644
--- a/lib/Target/PowerPC/PPCScheduleE5500.td
+++ b/lib/Target/PowerPC/PPCScheduleE5500.td
@@ -170,6 +170,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
[7, 2], // Latency = 3, Repeat rate = 1
[E5500_GPR_Bypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
+ InstrStage<1, [E5500_LSU_0]>],
+ [7, 2], // Latency = 3, Repeat rate = 1
+ [E5500_GPR_Bypass, E5500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStLD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
@@ -184,6 +190,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
[7, 2], // Latency = 3, Repeat rate = 1
[E5500_GPR_Bypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStLDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
+ InstrStage<1, [E5500_LSU_0]>],
+ [7, 2], // Latency = 3, Repeat rate = 1
+ [E5500_GPR_Bypass, E5500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStStore, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
@@ -223,6 +235,13 @@ def PPCE5500Itineraries : ProcessorItineraries<
[E5500_FPR_Bypass,
E5500_GPR_Bypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
+ InstrStage<1, [E5500_LSU_0]>],
+ [8, 2, 2], // Latency = 4, Repeat rate = 1
+ [E5500_FPR_Bypass,
+ E5500_GPR_Bypass, E5500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3
@@ -233,6 +252,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
[7, 2], // Latency = 3, Repeat rate = 1
[E5500_GPR_Bypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
+ InstrStage<1, [E5500_LSU_0]>],
+ [7, 2], // Latency = 3, Repeat rate = 1
+ [E5500_GPR_Bypass, E5500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<4, [E5500_LSU_0]>],
[8, 2], // Latency = r+3, Repeat rate = r+3
@@ -256,6 +281,12 @@ def PPCE5500Itineraries : ProcessorItineraries<
[7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, E5500_GPR_Bypass],
2>, // 2 micro-ops
+ InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
+ InstrStage<1, [E5500_LSU_0]>],
+ [7, 2], // Latency = 3, Repeat rate = 1
+ [NoBypass, E5500_GPR_Bypass],
+ 2>, // 2 micro-ops
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
@@ -272,6 +303,10 @@ def PPCE5500Itineraries : ProcessorItineraries<
InstrStage<5, [E5500_CFX_0]>],
[9, 2], // Latency = 5, Repeat rate = 5
[E5500_GPR_Bypass, E5500_CR_Bypass]>,
+ InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
+ InstrStage<5, [E5500_CFX_0]>],
+ [9, 2], // Latency = 5, Repeat rate = 5
+ [E5500_GPR_Bypass, E5500_CR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<4, [E5500_SFX0]>],
[8, 2], // Latency = 4, Repeat rate = 4
diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td
index c619297f22..21efd8f8f6 100644
--- a/lib/Target/PowerPC/PPCScheduleG3.td
+++ b/lib/Target/PowerPC/PPCScheduleG3.td
@@ -41,6 +41,7 @@ def G3Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G3_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G3_SLU]>]>,
+ InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStICBI , [InstrStage<3, [G3_SLU]>]>,
@@ -48,8 +49,10 @@ def G3Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLFD , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G3_SLU]>]>,
+ InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLHA , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G3_SLU]>]>,
+ InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStLMW , [InstrStage<34, [G3_SLU]>]>,
InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G3_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [G3_SLU]>]>,
diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td
index 2b282bfa53..340773ef78 100644
--- a/lib/Target/PowerPC/PPCScheduleG4.td
+++ b/lib/Target/PowerPC/PPCScheduleG4.td
@@ -46,6 +46,7 @@ def G4Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStDCBI , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G4_SLU]>]>,
+ InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<2, [G4_SLU]>]>,
@@ -54,8 +55,10 @@ def G4Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLFD , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G4_SLU]>]>,
+ InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLHA , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G4_SLU]>]>,
+ InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLMW , [InstrStage<34, [G4_SLU]>]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<2, [G4_SLU]>]>,
InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4_SLU]>]>,
diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td
index 9aaca5dc25..1d9f13fcb8 100644
--- a/lib/Target/PowerPC/PPCScheduleG4Plus.td
+++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td
@@ -54,6 +54,7 @@ def G4PlusItineraries : ProcessorItineraries<
InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>,
+ InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>,
@@ -62,8 +63,10 @@ def G4PlusItineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLFD , [InstrStage<4, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<4, [G4P_SLU]>]>,
+ InstrItinData<IIC_LdStLFDUX , [InstrStage<4, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLHA , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<3, [G4P_SLU]>]>,
+ InstrItinData<IIC_LdStLHAUX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLMW , [InstrStage<37, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStLWA , [InstrStage<3, [G4P_SLU]>]>,
@@ -71,6 +74,7 @@ def G4PlusItineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G4P_SLU]>]>,
+ InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>,
InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>,
diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td
index 2329e58b1c..a3b73ab445 100644
--- a/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/lib/Target/PowerPC/PPCScheduleG5.td
@@ -52,6 +52,7 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,
+ InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>,
@@ -60,11 +61,14 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>,
InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>,
+ InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>,
+ InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>,
+ InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>,
@@ -73,6 +77,7 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G5_SLU]>]>,
+ InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>,
@@ -83,6 +88,7 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>,
InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>,
+ InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>,
InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>,
InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>,
InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>,
@@ -95,7 +101,8 @@ def G5Itineraries : ProcessorItineraries<
InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
- InstrItinData<IIC_FPSqrt , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
+ InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
+ InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>,
InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>,
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 12:01:08 +0000