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author | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-18 08:13:05 +0000 |
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committer | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-18 08:13:05 +0000 |
commit | beb920fce6ccc89b4735f280f94cb8c227f4ef5e (patch) | |
tree | b05f8b29168dcdff8045ea3d5b0f859beab8b8a0 | |
parent | f8b60d6f30a8f25c84a71d36ff3a86fe1f52f671 (diff) | |
download | llvm-beb920fce6ccc89b4735f280f94cb8c227f4ef5e.tar.gz llvm-beb920fce6ccc89b4735f280f94cb8c227f4ef5e.tar.bz2 llvm-beb920fce6ccc89b4735f280f94cb8c227f4ef5e.tar.xz |
ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly
This patch also makes the assembler look at the .w/.n specifier for
loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 6 | ||||
-rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 4 | ||||
-rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 2 | ||||
-rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 21 |
4 files changed, 27 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 8e19d32aca..2693f32904 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1024,16 +1024,16 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc, def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, opc, ".w\t$Rt, $addr", [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> { + bits<4> Rt; + bits<13> addr; let isReMaterializable = 1; let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = signed; - let Inst{23} = ?; // add = (U == '1') + let Inst{23} = addr{12}; // add = (U == '1') let Inst{22-21} = opcod; let Inst{20} = 1; // load let Inst{19-16} = 0b1111; // Rn - bits<4> Rt; - bits<12> addr; let Inst{15-12} = Rt{3-0}; let Inst{11-0} = addr{11-0}; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index e315d16574..170d434744 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5862,7 +5862,9 @@ processInstruction(MCInst &Inst, case ARM::t2LDRpcrel: // Select the narrow version if the immediate will fit. if (Inst.getOperand(1).getImm() > 0 && - Inst.getOperand(1).getImm() <= 0xff) + Inst.getOperand(1).getImm() <= 0xff && + !(static_cast<ARMOperand*>(Operands[2])->isToken() && + static_cast<ARMOperand*>(Operands[2])->getToken() == ".w")) Inst.setOpcode(ARM::tLDRpci); else Inst.setOpcode(ARM::t2LDRpci); diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index f324bc2e37..8631d81ea0 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -743,10 +743,10 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, if (!MO.isReg()) { Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. Imm12 = 0; - isAdd = false ; // 'U' bit is set as part of the fixup. if (MO.isExpr()) { const MCExpr *Expr = MO.getExpr(); + isAdd = false ; // 'U' bit is set as part of the fixup. MCFixupKind Kind; if (isThumb2()) diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 978ec8298d..9eb9244faa 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -3515,12 +3515,31 @@ _func: @------------------------------------------------------------------------------ @ Alternate syntax for LDR*(literal) encodings @------------------------------------------------------------------------------ + ldrb r11, [pc, #22] + ldrh r11, [pc, #22] + ldrsb r11, [pc, #22] + ldrsh r11, [pc, #22] + ldr.w r11, [pc, #22] + ldrb.w r11, [pc, #22] + ldrh.w r11, [pc, #22] + ldrsb.w r11, [pc, #22] + ldrsh.w r11, [pc, #22] + +@ CHECK: ldrb.w r11, [pc, #22] @ encoding: [0x9f,0xf8,0x16,0xb0] +@ CHECK: ldrh.w r11, [pc, #22] @ encoding: [0xbf,0xf8,0x16,0xb0] +@ CHECK: ldrsb.w r11, [pc, #22] @ encoding: [0x9f,0xf9,0x16,0xb0] +@ CHECK: ldrsh.w r11, [pc, #22] @ encoding: [0xbf,0xf9,0x16,0xb0] +@ CHECK: ldr.w r11, [pc, #22] @ encoding: [0xdf,0xf8,0x16,0xb0] +@ CHECK: ldrb.w r11, [pc, #22] @ encoding: [0x9f,0xf8,0x16,0xb0] +@ CHECK: ldrh.w r11, [pc, #22] @ encoding: [0xbf,0xf8,0x16,0xb0] +@ CHECK: ldrsb.w r11, [pc, #22] @ encoding: [0x9f,0xf9,0x16,0xb0] +@ CHECK: ldrsh.w r11, [pc, #22] @ encoding: [0xbf,0xf9,0x16,0xb0] + ldr r11, [pc, #-22] ldrb r11, [pc, #-22] ldrh r11, [pc, #-22] ldrsb r11, [pc, #-22] ldrsh r11, [pc, #-22] - ldr.w r11, [pc, #-22] ldrb.w r11, [pc, #-22] ldrh.w r11, [pc, #-22] |