diff options
| author | Michael Liao <michael.liao@intel.com> | 2013-10-15 17:51:58 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2013-10-15 17:51:58 +0000 |
| commit | bfa7b1e6955ce3cc83214c253696470cef6db179 (patch) | |
| tree | 523f13ce40247817d9ef32978d2fb04343dc8d20 | |
| parent | dc8c044a9a3e00cab52ca204717de7aee9dab1be (diff) | |
| download | llvm-bfa7b1e6955ce3cc83214c253696470cef6db179.tar.gz llvm-bfa7b1e6955ce3cc83214c253696470cef6db179.tar.bz2 llvm-bfa7b1e6955ce3cc83214c253696470cef6db179.tar.xz | |
Fix PR17546
- Type of index used in extract_vector_elt or insert_vector_elt supposes
to be TLI.getVectorIdxTy() which is pointer type on most targets. It'd
better to truncate (or zero-extend in case it's changed later) it to
mask element type to guarantee they are matching instead of asserting
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192722 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/X86/pr17546.ll | 10 |
2 files changed, 11 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 8e3a4d747a..54d824419f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -7627,12 +7627,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() / MaskEltVT.getSizeInBits()); - if (Idx.getSimpleValueType() != MaskEltVT) - if (Idx.getOpcode() == ISD::ZERO_EXTEND || - Idx.getOpcode() == ISD::SIGN_EXTEND) - Idx = Idx.getOperand(0); - assert(Idx.getSimpleValueType() == MaskEltVT && - "Unexpected index in insertelement"); + Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT); SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT, getZeroVector(MaskVT, Subtarget, DAG, dl), Idx, DAG.getConstant(0, getPointerTy())); diff --git a/test/CodeGen/X86/pr17546.ll b/test/CodeGen/X86/pr17546.ll new file mode 100644 index 0000000000..174fa5ca3f --- /dev/null +++ b/test/CodeGen/X86/pr17546.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core-avx2 | FileCheck %s + +define i32 @f_f___un_3C_unf_3E_un_3C_unf_3E_(<8 x i32> %__mask, i64 %BBBB) { + %QQQ = trunc i64 %BBBB to i32 + %1 = extractelement <8 x i32> %__mask, i32 %QQQ + ret i32 %1 +} + +; CHECK: f_f___un_3C_unf_3E_un_3C_unf_3E_ +; CHECK: ret |