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| author | Richard Osborne <richard@xmos.com> | 2011-07-19 13:28:50 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2011-07-19 13:28:50 +0000 |
| commit | c8007ab582c49bb6d165e09e6279e441af985ecf (patch) | |
| tree | ef4ff900f8aec8041aff378933dab10b56757c43 | |
| parent | 829bef1a467e1049c8dc412167c5da6f63a398e2 (diff) | |
| download | llvm-c8007ab582c49bb6d165e09e6279e441af985ecf.tar.gz llvm-c8007ab582c49bb6d165e09e6279e441af985ecf.tar.bz2 llvm-c8007ab582c49bb6d165e09e6279e441af985ecf.tar.xz | |
Add intrinsics for the zext / sext instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/IntrinsicsXCore.td | 4 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 20 | ||||
| -rw-r--r-- | test/CodeGen/XCore/misc-intrinsics.ll | 30 |
3 files changed, 47 insertions, 7 deletions
diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td index 199b66648c..93f555da0e 100644 --- a/include/llvm/IntrinsicsXCore.td +++ b/include/llvm/IntrinsicsXCore.td @@ -17,6 +17,10 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". def int_xcore_crc32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], [IntrNoMem]>; + def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], + [IntrNoMem]>; + def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], + [IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index db05fff5a9..d310a51048 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -754,7 +754,7 @@ def BL_lu10 : _FLU10< } // Two operand short -// TODO eet, eef, tsetmr, sext (reg), zext (reg) +// TODO eet, eef, tsetmr def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; @@ -764,15 +764,21 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), [(set GRRegs:$dst, (ineg GRRegs:$b))]>; let Constraints = "$src1 = $dst" in { -let neverHasSideEffects = 1 in def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), - "sext $dst, $src2", - []>; + "sext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, immBitp:$src2))]>; + +def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "sext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; -let neverHasSideEffects = 1 in def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), - "zext $dst, $src2", - []>; + "zext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, immBitp:$src2))]>; + +def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "zext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "andnot $dst, $src2", diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll index f504a2ed72..458f23f28f 100644 --- a/test/CodeGen/XCore/misc-intrinsics.ll +++ b/test/CodeGen/XCore/misc-intrinsics.ll @@ -4,6 +4,8 @@ declare i32 @llvm.xcore.bitrev(i32) declare i32 @llvm.xcore.crc32(i32, i32, i32) declare %0 @llvm.xcore.crc8(i32, i32, i32) +declare i32 @llvm.xcore.zext(i32, i32) +declare i32 @llvm.xcore.sext(i32, i32) define i32 @bitrev(i32 %val) { ; CHECK: bitrev: @@ -25,3 +27,31 @@ define %0 @crc8(i32 %crc, i32 %data, i32 %poly) { %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) ret %0 %result } + +define i32 @zext(i32 %a, i32 %b) { +; CHECK: zext: +; CHECK: zext r0, r1 + %result = call i32 @llvm.xcore.zext(i32 %a, i32 %b) + ret i32 %result +} + +define i32 @zexti(i32 %a) { +; CHECK: zexti: +; CHECK: zext r0, 4 + %result = call i32 @llvm.xcore.zext(i32 %a, i32 4) + ret i32 %result +} + +define i32 @sext(i32 %a, i32 %b) { +; CHECK: sext: +; CHECK: sext r0, r1 + %result = call i32 @llvm.xcore.sext(i32 %a, i32 %b) + ret i32 %result +} + +define i32 @sexti(i32 %a) { +; CHECK: sexti: +; CHECK: sext r0, 4 + %result = call i32 @llvm.xcore.sext(i32 %a, i32 4) + ret i32 %result +} |