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| author | Cameron Zwarich <zwarich@apple.com> | 2011-04-15 20:28:28 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-04-15 20:28:28 +0000 |
| commit | ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41f (patch) | |
| tree | 9b6631b0f0408e53862d718106fa38ccd6ee399d | |
| parent | 99a2e98eddf00c4afd3817564cb8c914a6f66ae9 (diff) | |
| download | llvm-ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41f.tar.gz llvm-ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41f.tar.bz2 llvm-ca3f6a3925e9a6e91022aa211bdc1b6e3f2ff41f.tar.xz | |
Add missing register forms of instructions to the ARM CMP-folding code. This
fixes <rdar://problem/9287901>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll | 22 |
2 files changed, 34 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index af51fe7989..e2eeeed8ce 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1618,16 +1618,26 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, // Set the "zero" bit in CPSR. switch (MI->getOpcode()) { default: break; + case ARM::RSBrr: case ARM::RSBri: + case ARM::RSCrr: case ARM::RSCri: + case ARM::ADDrr: case ARM::ADDri: + case ARM::ADCrr: case ARM::ADCri: + case ARM::SUBrr: case ARM::SUBri: + case ARM::SBCrr: case ARM::SBCri: case ARM::t2RSBri: + case ARM::t2ADDrr: case ARM::t2ADDri: + case ARM::t2ADCrr: case ARM::t2ADCri: + case ARM::t2SUBrr: case ARM::t2SUBri: + case ARM::t2SBCrr: case ARM::t2SBCri: { // Scan forward for the use of CPSR, if it's a conditional code requires // checking of V bit, then this is not safe to do. If we can't find the @@ -1669,7 +1679,9 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, // fallthrough } + case ARM::ANDrr: case ARM::ANDri: + case ARM::t2ANDrr: case ARM::t2ANDri: // Toggle the optional operand to CPSR. MI->getOperand(5).setReg(ARM::CPSR); diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll new file mode 100644 index 0000000000..a98d3f6ba9 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s + +; CHECK: _f +; CHECK: adds +; CHECK-NOT: cmp +; CHECK: blxeq _g + +define i32 @f(i32 %a, i32 %b) nounwind ssp { +entry: + %add = add nsw i32 %b, %a + %cmp = icmp eq i32 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @g(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %add +} + +declare void @g(...) |