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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-18 00:36:21 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-18 00:36:21 +0000 |
| commit | cfe02c46dc7b97adb3c76ce46bc24aff3266df34 (patch) | |
| tree | e3b3a6fd2bcd8c9ad25124121a3df7712a1ee39e | |
| parent | e89024e4f91faa6d8e834feb725dd964d7aeff42 (diff) | |
| download | llvm-cfe02c46dc7b97adb3c76ce46bc24aff3266df34.tar.gz llvm-cfe02c46dc7b97adb3c76ce46bc24aff3266df34.tar.bz2 llvm-cfe02c46dc7b97adb3c76ce46bc24aff3266df34.tar.xz | |
R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206541 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/R600/extload.ll | 9 | ||||
| -rw-r--r-- | test/CodeGen/R600/zero_extend.ll | 7 |
3 files changed, 11 insertions, 7 deletions
diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index 574bef2cca..3c41638b7c 100644 --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -351,7 +351,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) { SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32); SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32); } else if (N->getValueType(0) == MVT::i64) { - RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32); + RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32); SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32); SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32); } else { diff --git a/test/CodeGen/R600/extload.ll b/test/CodeGen/R600/extload.ll index 2e70d47047..daa76857a1 100644 --- a/test/CodeGen/R600/extload.ll +++ b/test/CodeGen/R600/extload.ll @@ -87,8 +87,9 @@ define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1) } ; FUNC-LABEL: @zextload_global_i8_to_i64 +; SI: S_MOV_B32 [[ZERO:s[0-9]+]], 0 ; SI: BUFFER_LOAD_UBYTE [[LOAD:v[0-9]+]], -; SI: V_MOV_B32_e32 {{v[0-9]+}}, 0 +; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]] ; SI: BUFFER_STORE_DWORDX2 define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { %a = load i8 addrspace(1)* %in, align 8 @@ -98,8 +99,9 @@ define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* } ; FUNC-LABEL: @zextload_global_i16_to_i64 +; SI: S_MOV_B32 [[ZERO:s[0-9]+]], 0 ; SI: BUFFER_LOAD_USHORT [[LOAD:v[0-9]+]], -; SI: V_MOV_B32_e32 {{v[0-9]+}}, 0 +; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]] ; SI: BUFFER_STORE_DWORDX2 define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { %a = load i16 addrspace(1)* %in, align 8 @@ -109,8 +111,9 @@ define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1) } ; FUNC-LABEL: @zextload_global_i32_to_i64 +; SI: S_MOV_B32 [[ZERO:s[0-9]+]], 0 ; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]], -; SI: V_MOV_B32_e32 {{v[0-9]+}}, 0 +; SI: V_MOV_B32_e32 {{v[0-9]+}}, [[ZERO]] ; SI: BUFFER_STORE_DWORDX2 define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %a = load i32 addrspace(1)* %in, align 8 diff --git a/test/CodeGen/R600/zero_extend.ll b/test/CodeGen/R600/zero_extend.ll index c561ff7428..8585d4ab19 100644 --- a/test/CodeGen/R600/zero_extend.ll +++ b/test/CodeGen/R600/zero_extend.ll @@ -6,8 +6,9 @@ ; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW ; SI-CHECK: @test -; SI-CHECK: V_MOV_B32_e32 v[[ZERO:[0-9]]], 0 -; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[ZERO]]{{\]}} +; SI-CHECK: S_MOV_B32 [[ZERO:s[0-9]]], 0 +; SI-CHECK: V_MOV_B32_e32 v[[V_ZERO:[0-9]]], [[ZERO]] +; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[V_ZERO]]{{\]}} define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { entry: %0 = mul i32 %a, %b @@ -30,7 +31,7 @@ entry: ; SI-CHECK-LABEL: @zext_i1_to_i64 ; SI-CHECK: V_CMP_EQ_I32 ; SI-CHECK: V_CNDMASK_B32 -; SI-CHECK: V_MOV_B32_e32 v{{[0-9]+}}, 0 +; SI-CHECK: S_MOV_B32 s{{[0-9]+}}, 0 define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %ext = zext i1 %cmp to i64 |