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| author | Chris Lattner <sabre@nondot.org> | 2008-02-27 05:47:54 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-02-27 05:47:54 +0000 |
| commit | d0ba2a9c146df8deb355fd5e375f52671109600f (patch) | |
| tree | 8be940e034d6e97828cebb2c98fd336a19a5ed03 | |
| parent | d36531249a9a9500e516148e7e72d4c0a7a4d0ee (diff) | |
| download | llvm-d0ba2a9c146df8deb355fd5e375f52671109600f.tar.gz llvm-d0ba2a9c146df8deb355fd5e375f52671109600f.tar.bz2 llvm-d0ba2a9c146df8deb355fd5e375f52671109600f.tar.xz | |
Compile x86-64-and-mask.ll into:
_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47658 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/README-X86-64.txt | 11 | ||||
| -rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 13 | ||||
| -rw-r--r-- | test/CodeGen/X86/x86-64-and-mask.ll | 12 |
3 files changed, 26 insertions, 10 deletions
diff --git a/lib/Target/X86/README-X86-64.txt b/lib/Target/X86/README-X86-64.txt index bdff56d40b..59cecdf4f2 100644 --- a/lib/Target/X86/README-X86-64.txt +++ b/lib/Target/X86/README-X86-64.txt @@ -249,15 +249,6 @@ _a: addq $8, %rsp ret -note the dead rsp adjustments. Also, there is surely a better/shorter way -to clear the top 32-bits of a 64-bit register than movl+andq. Testcase here: - -unsigned long long c(unsigned long long a) {return a&4294967295; } - -_c: - movl $4294967295, %ecx - movq %rdi, %rax - andq %rcx, %rax - ret +note the dead rsp adjustments. //===---------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 5c7f093f6a..04a76d5d17 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -61,6 +61,13 @@ def i64immSExt8 : PatLeaf<(i64 imm), [{ return (int64_t)N->getValue() == (int8_t)N->getValue(); }]>; +def i64immFFFFFFFF : PatLeaf<(i64 imm), [{ + // i64immFFFFFFFF - True if this is a specific constant we can't write in + // tblgen files. + return N->getValue() == 0x00000000FFFFFFFFULL; +}]>; + + def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; @@ -1091,6 +1098,12 @@ def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>; +/// PsAND64rrFFFFFFFF - r = r & (2^32-1) +def PsAND64rrFFFFFFFF + : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), + "mov{l}\t{${src:subreg32}, ${dst:subreg32}|${dst:subreg32}, ${src:subreg32}}", + [(set GR64:$dst, (and GR64:$src, i64immFFFFFFFF))]>; + // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's // equivalent due to implicit zero-extending, and it sometimes has a smaller diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll new file mode 100644 index 0000000000..3d61e5dbe5 --- /dev/null +++ b/test/CodeGen/X86/x86-64-and-mask.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc | grep {movl.*%edi, %eax} +; This should be a single mov, not a load of immediate + andq. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin8" + +define i64 @test(i64 %x) nounwind { +entry: + %tmp123 = and i64 %x, 4294967295 ; <i64> [#uses=1] + ret i64 %tmp123 +} + |