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author | Andrew Trick <atrick@apple.com> | 2012-03-07 23:00:59 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-03-07 23:00:59 +0000 |
commit | d790cada339d7af81650084b9bb6b2ad65566fbb (patch) | |
tree | 748ecb4d8f4cdc0d7caa6deccb5dedd6332bb666 | |
parent | 035ec40eaf1dcd8f4809fb183098259f2dec75b9 (diff) | |
download | llvm-d790cada339d7af81650084b9bb6b2ad65566fbb.tar.gz llvm-d790cada339d7af81650084b9bb6b2ad65566fbb.tar.bz2 llvm-d790cada339d7af81650084b9bb6b2ad65566fbb.tar.xz |
misched prep: Comment the ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 5 | ||||
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.h | 19 |
2 files changed, 15 insertions, 9 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index c4addeea25..d2351a371f 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -38,8 +38,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, bool IsPostRAFlag, LiveIntervals *lis) : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), - InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag), - LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) { + InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis), + IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT), + FirstDbgValue(0) { assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); DbgValues.clear(); assert(!(IsPostRA && MRI.getNumVirtRegs()) && diff --git a/lib/CodeGen/ScheduleDAGInstrs.h b/lib/CodeGen/ScheduleDAGInstrs.h index 714de4eeff..27fb11c2fc 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.h +++ b/lib/CodeGen/ScheduleDAGInstrs.h @@ -171,16 +171,20 @@ namespace llvm { const MachineFrameInfo *MFI; const InstrItineraryData *InstrItins; + /// Live Intervals provides reaching defs in preRA scheduling. + LiveIntervals *LIS; + /// isPostRA flag indicates vregs cannot be present. bool IsPostRA; - /// Live Intervals provides reaching defs in preRA scheduling. - LiveIntervals *LIS; + /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using + /// the def-side latency only. + bool UnitLatencies; /// State specific to the current scheduling region. - /// + /// ------------------------------------------------ - // The block in which to insert instructions + /// The block in which to insert instructions MachineBasicBlock *BB; /// The beginning of the range to be scheduled. @@ -196,9 +200,8 @@ namespace llvm { /// scheduling region is mapped to an SUnit. DenseMap<MachineInstr*, SUnit*> MISUnitMap; - /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using - /// the def-side latency only. - bool UnitLatencies; + /// State internal to DAG building. + /// ------------------------------- /// Defs, Uses - Remember where defs and uses of each register are as we /// iterate upward through the instructions. This is allocated here instead @@ -220,6 +223,8 @@ namespace llvm { LoopDependencies LoopRegs; /// DbgValues - Remember instruction that preceeds DBG_VALUE. + /// These are generated by buildSchedGraph but persist so they can be + /// referenced when emitting the final schedule. typedef std::vector<std::pair<MachineInstr *, MachineInstr *> > DbgValueVector; DbgValueVector DbgValues; |