AArch64/ARM64: use HS instead of CS & LO instead of CC.

On instructions using the NZCV register, a couple of conditions have dual
representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and
unsigned-lower/carry-clear). The first of these is more descriptive in most
circumstances, so we should print it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207644 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 44 insertions, 44 deletions

diff --git a/lib/Target/ARM64/ARM64FastISel.cpp b/lib/Target/ARM64/ARM64FastISel.cpp
index cadd960b8c..0fce1cc64e 100644
--- a/lib/Target/ARM64/ARM64FastISel.cpp
+++ b/lib/Target/ARM64/ARM64FastISel.cpp
@@ -737,9 +737,9 @@ static ARM64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
   case CmpInst::ICMP_NE:
     return ARM64CC::NE;
   case CmpInst::ICMP_UGE:
-    return ARM64CC::CS;
+    return ARM64CC::HS;
   case CmpInst::ICMP_ULT:
-    return ARM64CC::CC;
+    return ARM64CC::LO;
   }
 }
 
diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp
index 869efcb4d4..029112986e 100644
--- a/lib/Target/ARM64/ARM64ISelLowering.cpp
+++ b/lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -822,9 +822,9 @@ static ARM64CC::CondCode changeIntCCToARM64CC(ISD::CondCode CC) {
   case ISD::SETUGT:
     return ARM64CC::HI;
   case ISD::SETUGE:
-    return ARM64CC::CS;
+    return ARM64CC::HS;
   case ISD::SETULT:
-    return ARM64CC::CC;
+    return ARM64CC::LO;
   case ISD::SETULE:
     return ARM64CC::LS;
   }
@@ -1052,7 +1052,7 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
     break;
   case ISD::UADDO:
     Opc = ARM64ISD::ADDS;
-    CC = ARM64CC::CS;
+    CC = ARM64CC::HS;
     break;
   case ISD::SSUBO:
     Opc = ARM64ISD::SUBS;
@@ -1060,7 +1060,7 @@ getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
     break;
   case ISD::USUBO:
     Opc = ARM64ISD::SUBS;
-    CC = ARM64CC::CC;
+    CC = ARM64CC::LO;
     break;
   // Multiply needs a little bit extra work.
   case ISD::SMULO:
@@ -5553,7 +5553,7 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
     return DAG.getNode(ARM64ISD::CMGE, dl, VT, RHS, LHS);
   case ARM64CC::LS:
     return DAG.getNode(ARM64ISD::CMHS, dl, VT, RHS, LHS);
-  case ARM64CC::CC:
+  case ARM64CC::LO:
     return DAG.getNode(ARM64ISD::CMHI, dl, VT, RHS, LHS);
   case ARM64CC::LT:
     if (IsZero)
@@ -5561,7 +5561,7 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
     return DAG.getNode(ARM64ISD::CMGT, dl, VT, RHS, LHS);
   case ARM64CC::HI:
     return DAG.getNode(ARM64ISD::CMHI, dl, VT, LHS, RHS);
-  case ARM64CC::CS:
+  case ARM64CC::HS:
     return DAG.getNode(ARM64ISD::CMHS, dl, VT, LHS, RHS);
   }
 }
diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index cfe9ae08ac..3df5b8b708 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -2221,10 +2221,10 @@ unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
   unsigned CC = StringSwitch<unsigned>(Cond.lower())
                     .Case("eq", ARM64CC::EQ)
                     .Case("ne", ARM64CC::NE)
-                    .Case("cs", ARM64CC::CS)
-                    .Case("hs", ARM64CC::CS)
-                    .Case("cc", ARM64CC::CC)
-                    .Case("lo", ARM64CC::CC)
+                    .Case("cs", ARM64CC::HS)
+                    .Case("hs", ARM64CC::HS)
+                    .Case("cc", ARM64CC::LO)
+                    .Case("lo", ARM64CC::LO)
                     .Case("mi", ARM64CC::MI)
                     .Case("pl", ARM64CC::PL)
                     .Case("vs", ARM64CC::VS)
diff --git a/lib/Target/ARM64/Utils/ARM64BaseInfo.h b/lib/Target/ARM64/Utils/ARM64BaseInfo.h
index 66c2052e62..ef4caefab9 100644
--- a/lib/Target/ARM64/Utils/ARM64BaseInfo.h
+++ b/lib/Target/ARM64/Utils/ARM64BaseInfo.h
@@ -192,8 +192,8 @@ namespace ARM64CC {
 enum CondCode {  // Meaning (integer)          Meaning (floating-point)
   EQ = 0x0,      // Equal                      Equal
   NE = 0x1,      // Not equal                  Not equal, or unordered
-  CS = 0x2,      // Carry set                  >, ==, or unordered
-  CC = 0x3,      // Carry clear                Less than
+  HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
+  LO = 0x3,      // Unsigned lower             Less than
   MI = 0x4,      // Minus, negative            Less than
   PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
   VS = 0x6,      // Overflow                   Unordered
@@ -215,8 +215,8 @@ inline static const char *getCondCodeName(CondCode Code) {
   default: llvm_unreachable("Unknown condition code");
   case EQ:  return "eq";
   case NE:  return "ne";
-  case CS:  return "cs";
-  case CC:  return "cc";
+  case HS:  return "hs";
+  case LO:  return "lo";
   case MI:  return "mi";
   case PL:  return "pl";
   case VS:  return "vs";
@@ -237,8 +237,8 @@ inline static CondCode getInvertedCondCode(CondCode Code) {
   default: llvm_unreachable("Unknown condition code");
   case EQ:  return NE;
   case NE:  return EQ;
-  case CS:  return CC;
-  case CC:  return CS;
+  case HS:  return LO;
+  case LO:  return HS;
   case MI:  return PL;
   case PL:  return MI;
   case VS:  return VC;
@@ -263,8 +263,8 @@ inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
   default: llvm_unreachable("Unknown condition code");
   case EQ: return Z; // Z == 1
   case NE: return 0; // Z == 0
-  case CS: return C; // C == 1
-  case CC: return 0; // C == 0
+  case HS: return C; // C == 1
+  case LO: return 0; // C == 0
   case MI: return N; // N == 1
   case PL: return 0; // N == 0
   case VS: return V; // V == 1
diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll
index f9c1cc0dd5..b64ad2a83d 100644
--- a/test/CodeGen/AArch64/addsub.ll
+++ b/test/CodeGen/AArch64/addsub.ll
@@ -87,7 +87,7 @@ define void @testing() {
 
 test2:
 ; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-; CHECK: b.{{cc|lo}} [[RET]]
+; CHECK: b.lo [[RET]]
   %newval2 = add i32 %val, 1
   store i32 %newval2, i32* @var_i32
   %cmp_pos_big = icmp ult i32 %val, 14610432
diff --git a/test/CodeGen/ARM64/fast-isel-icmp.ll b/test/CodeGen/ARM64/fast-isel-icmp.ll
index 22af5428d9..68a76c9e3e 100644
--- a/test/CodeGen/ARM64/fast-isel-icmp.ll
+++ b/test/CodeGen/ARM64/fast-isel-icmp.ll
@@ -54,7 +54,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {
 entry:
 ; CHECK: icmp_uge
 ; CHECK: cmp  w0, w1
-; CHECK: csinc w0, wzr, wzr, cc
+; CHECK: csinc w0, wzr, wzr, lo
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
@@ -64,7 +64,7 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {
 entry:
 ; CHECK: icmp_ult
 ; CHECK: cmp  w0, w1
-; CHECK: csinc w0, wzr, wzr, cs
+; CHECK: csinc w0, wzr, wzr, hs
   %cmp = icmp ult i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
@@ -158,7 +158,7 @@ entry:
 ; CHECK: uxth w0, w0
 ; CHECK: uxth w1, w1
 ; CHECK: cmp  w0, w1
-; CHECK: csinc w0, wzr, wzr, cs
+; CHECK: csinc w0, wzr, wzr, hs
   %cmp = icmp ult i16 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
@@ -206,7 +206,7 @@ entry:
 ; CHECK: icmp_i1_unsigned_const
 ; CHECK: and w0, w0, #0x1
 ; CHECK: cmp  w0, #0
-; CHECK: csinc w0, wzr, wzr, cs
+; CHECK: csinc w0, wzr, wzr, hs
 ; CHECK: and w0, w0, #0x1
   %cmp = icmp ult i1 %a, 0
   %conv2 = zext i1 %cmp to i32
diff --git a/test/CodeGen/ARM64/xaluo.ll b/test/CodeGen/ARM64/xaluo.ll
index 6a8520d1c1..bda41b10c3 100644
--- a/test/CodeGen/ARM64/xaluo.ll
+++ b/test/CodeGen/ARM64/xaluo.ll
@@ -31,7 +31,7 @@ define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
 entry:
 ; CHECK-LABEL:  uaddo.i32
 ; CHECK:        adds w8, w0, w1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cc
+; CHECK-NEXT:   csinc w0, wzr, wzr, lo
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -43,7 +43,7 @@ define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
 entry:
 ; CHECK-LABEL:  uaddo.i64
 ; CHECK:        adds x8, x0, x1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cc
+; CHECK-NEXT:   csinc w0, wzr, wzr, lo
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
@@ -79,7 +79,7 @@ define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
 entry:
 ; CHECK-LABEL:  usubo.i32
 ; CHECK:        subs w8, w0, w1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cs
+; CHECK-NEXT:   csinc w0, wzr, wzr, hs
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -91,7 +91,7 @@ define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
 entry:
 ; CHECK-LABEL:  usubo.i64
 ; CHECK:        subs x8, x0, x1
-; CHECK-NEXT:   csinc w0, wzr, wzr, cs
+; CHECK-NEXT:   csinc w0, wzr, wzr, hs
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
@@ -184,7 +184,7 @@ define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.select.i32
 ; CHECK:        cmn w0, w1
-; CHECK-NEXT:   csel w0, w0, w1, cs
+; CHECK-NEXT:   csel w0, w0, w1, hs
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
@@ -195,7 +195,7 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.select.i64
 ; CHECK:        cmn x0, x1
-; CHECK-NEXT:   csel x0, x0, x1, cs
+; CHECK-NEXT:   csel x0, x0, x1, hs
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
@@ -228,7 +228,7 @@ define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.select.i32
 ; CHECK:        cmp w0, w1
-; CHECK-NEXT:   csel w0, w0, w1, cc
+; CHECK-NEXT:   csel w0, w0, w1, lo
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2
@@ -239,7 +239,7 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.select.i64
 ; CHECK:        cmp x0, x1
-; CHECK-NEXT:   csel x0, x0, x1, cc
+; CHECK-NEXT:   csel x0, x0, x1, lo
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
@@ -338,7 +338,7 @@ define i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.br.i32
 ; CHECK:        cmn w0, w1
-; CHECK-NEXT:   b.cc
+; CHECK-NEXT:   b.lo
   %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -355,7 +355,7 @@ define i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.br.i64
 ; CHECK:        cmn x0, x1
-; CHECK-NEXT:   b.cc
+; CHECK-NEXT:   b.lo
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
@@ -406,7 +406,7 @@ define i1 @usubo.br.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.br.i32
 ; CHECK:        cmp w0, w1
-; CHECK-NEXT:   b.cs
+; CHECK-NEXT:   b.hs
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
@@ -423,7 +423,7 @@ define i1 @usubo.br.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.br.i64
 ; CHECK:        cmp x0, x1
-; CHECK-NEXT:   b.cs
+; CHECK-NEXT:   b.hs
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %val = extractvalue {i64, i1} %t, 0
   %obit = extractvalue {i64, i1} %t, 1
diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/ARM64/arithmetic-encoding.s
index 4b5e151f54..7a30e998cb 100644
--- a/test/MC/ARM64/arithmetic-encoding.s
+++ b/test/MC/ARM64/arithmetic-encoding.s
@@ -602,10 +602,10 @@ foo:
 
 ; CHECK: csel	w16, w7, w27, eq        ; encoding: [0xf0,0x00,0x9b,0x1a]
 ; CHECK: csel	w15, w6, w26, ne        ; encoding: [0xcf,0x10,0x9a,0x1a]
-; CHECK: csel	w14, w5, w25, cs        ; encoding: [0xae,0x20,0x99,0x1a]
-; CHECK: csel	w13, w4, w24, cs        ; encoding: [0x8d,0x20,0x98,0x1a]
-; CHECK: csel	w12, w3, w23, cc        ; encoding: [0x6c,0x30,0x97,0x1a]
-; CHECK: csel	w11, w2, w22, cc        ; encoding: [0x4b,0x30,0x96,0x1a]
+; CHECK: csel	w14, w5, w25, hs        ; encoding: [0xae,0x20,0x99,0x1a]
+; CHECK: csel	w13, w4, w24, hs        ; encoding: [0x8d,0x20,0x98,0x1a]
+; CHECK: csel	w12, w3, w23, lo        ; encoding: [0x6c,0x30,0x97,0x1a]
+; CHECK: csel	w11, w2, w22, lo        ; encoding: [0x4b,0x30,0x96,0x1a]
 ; CHECK: csel	w10, w1, w21, mi        ; encoding: [0x2a,0x40,0x95,0x1a]
 ; CHECK: csel	x9, x9, x1, pl          ; encoding: [0x29,0x51,0x81,0x9a]
 ; CHECK: csel	x8, x8, x2, vs          ; encoding: [0x08,0x61,0x82,0x9a]
diff --git a/test/MC/ARM64/branch-encoding.s b/test/MC/ARM64/branch-encoding.s
index 8f8751c2cc..ba8fb3d901 100644
--- a/test/MC/ARM64/branch-encoding.s
+++ b/test/MC/ARM64/branch-encoding.s
@@ -36,10 +36,10 @@ foo:
 ; CHECK: b.ne L1   ; encoding: [0bAAA00001,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.cs  L1
-; CHECK: b.cs L1   ; encoding: [0bAAA00010,A,A,0x54]
+; CHECK: b.hs L1   ; encoding: [0bAAA00010,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.cc  L1
-; CHECK: b.cc L1   ; encoding: [0bAAA00011,A,A,0x54]
+; CHECK: b.lo L1   ; encoding: [0bAAA00011,A,A,0x54]
 ; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch19
   b.mi  L1
 ; CHECK: b.mi L1   ; encoding: [0bAAA00100,A,A,0x54]
@@ -80,7 +80,7 @@ L1:
   b.lt #28
 ; CHECK: b.lt #28
   b.cc #1048572
-; CHECK: b.cc	#1048572                ; encoding: [0xe3,0xff,0x7f,0x54]
+; CHECK: b.lo	#1048572                ; encoding: [0xe3,0xff,0x7f,0x54]
   b #134217724
 ; CHECK: b	#134217724              ; encoding: [0xff,0xff,0xff,0x15]
   b #-134217728