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| author | Chandler Carruth <chandlerc@gmail.com> | 2011-12-24 11:11:38 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2011-12-24 11:11:38 +0000 |
| commit | d873a4b89b365f1e58e808109cd77034517f095d (patch) | |
| tree | 451529a10fe7ee2c369b9f7cf83c6a64e76f24ab | |
| parent | 131f7d35442416943309af1d13bf4462467181a1 (diff) | |
| download | llvm-d873a4b89b365f1e58e808109cd77034517f095d.tar.gz llvm-d873a4b89b365f1e58e808109cd77034517f095d.tar.bz2 llvm-d873a4b89b365f1e58e808109cd77034517f095d.tar.xz | |
Expand more when we have a nice 'tzcnt' instruction, to avoid generating
'bsf' instructions here.
This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/bmi.ll | 28 |
2 files changed, 32 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 47b12ee6a9..049e3cd842 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -382,6 +382,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Expand); if (Subtarget->hasBMI()) { setOperationAction(ISD::CTTZ , MVT::i8 , Promote); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); + if (Subtarget->is64Bit()) + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); } else { setOperationAction(ISD::CTTZ , MVT::i8 , Custom); setOperationAction(ISD::CTTZ , MVT::i16 , Custom); diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll index 261f24b03d..e79c92f1e2 100644 --- a/test/CodeGen/X86/bmi.ll +++ b/test/CodeGen/X86/bmi.ll @@ -33,6 +33,34 @@ define i64 @t4(i64 %x) nounwind { ; CHECK: tzcntq } +define i8 @t5(i8 %x) nounwind { + %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true ) + ret i8 %tmp +; CHECK: t5: +; CHECK: tzcntw +} + +define i16 @t6(i16 %x) nounwind { + %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true ) + ret i16 %tmp +; CHECK: t6: +; CHECK: tzcntw +} + +define i32 @t7(i32 %x) nounwind { + %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true ) + ret i32 %tmp +; CHECK: t7: +; CHECK: tzcntl +} + +define i64 @t8(i64 %x) nounwind { + %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true ) + ret i64 %tmp +; CHECK: t8: +; CHECK: tzcntq +} + define i32 @andn32(i32 %x, i32 %y) nounwind readnone { %tmp1 = xor i32 %x, -1 %tmp2 = and i32 %y, %tmp1 |