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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-21 20:08:32 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-21 20:08:32 +0000 |
| commit | db3461662e7945e04fe42e0d606581bba73c29dc (patch) | |
| tree | feeaf6846d0ccb96f145d1e9162c9b9b4d77af50 | |
| parent | 9e401f22ec4d1fc42c22802fef1479180ca31600 (diff) | |
| download | llvm-db3461662e7945e04fe42e0d606581bba73c29dc.tar.gz llvm-db3461662e7945e04fe42e0d606581bba73c29dc.tar.bz2 llvm-db3461662e7945e04fe42e0d606581bba73c29dc.tar.xz | |
Teach getVectorTypeBreakdown about promotion of vectors in addition to widening of vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155296 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/X86/2011-04-19-sclr-bb.ll | 21 |
2 files changed, 27 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index e341e15e41..a696d510b3 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -940,9 +940,12 @@ unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, unsigned NumElts = VT.getVectorNumElements(); // If there is a wider vector type with the same element type as this one, - // we should widen to that legal vector type. This handles things like - // <2 x float> -> <4 x float>. - if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { + // or a promoted vector type that has the same number of elements which + // are wider, then we should convert to that legal vector type. + // This handles things like <2 x float> -> <4 x float> and + // <4 x i1> -> <4 x i32>. + LegalizeTypeAction TA = getTypeAction(Context, VT); + if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { RegisterVT = getTypeToTransformTo(Context, VT); if (isTypeLegal(RegisterVT)) { IntermediateVT = RegisterVT; diff --git a/test/CodeGen/X86/2011-04-19-sclr-bb.ll b/test/CodeGen/X86/2011-04-19-sclr-bb.ll new file mode 100644 index 0000000000..771e4b3a08 --- /dev/null +++ b/test/CodeGen/X86/2011-04-19-sclr-bb.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s + +; Make sure that values of illegal types are not scalarized between basic blocks. +;CHECK: test +;CHECK-NOT: pinsrw +;CHECK-NOT: pextrb +;CHECK: ret +define void @test(i1 %cond) { +ENTRY: + br label %LOOP +LOOP: + %vec1 = phi <4 x i1> [ %vec1_or_2, %LOOP ], [ zeroinitializer, %ENTRY ] + %vec2 = phi <4 x i1> [ %vec2_and_1, %LOOP ], [ zeroinitializer, %ENTRY ] + %vec1_or_2 = or <4 x i1> %vec1, %vec2 + %vec2_and_1 = and <4 x i1> %vec2, %vec1 + br i1 %cond, label %LOOP, label %EXIT + +EXIT: + ret void +} + |