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author | NAKAMURA Takumi <geek4civic@gmail.com> | 2012-10-11 02:02:05 +0000 |
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committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2012-10-11 02:02:05 +0000 |
commit | e0297196edbe6539e7d3269fa19f84e04dd0a9cd (patch) | |
tree | 80b98b4a883f15c19b118c78dca752890f9c2d61 | |
parent | cea9264f6bcc00e5e9b696f5c098719a1461ec58 (diff) | |
download | llvm-e0297196edbe6539e7d3269fa19f84e04dd0a9cd.tar.gz llvm-e0297196edbe6539e7d3269fa19f84e04dd0a9cd.tar.bz2 llvm-e0297196edbe6539e7d3269fa19f84e04dd0a9cd.tar.xz |
Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."
It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 40 | ||||
-rw-r--r-- | test/CodeGen/X86/select_const.ll | 16 |
2 files changed, 0 insertions, 56 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9ff05a2d11..1580935fb2 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -14415,7 +14415,6 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { CC = X86::GetOppositeBranchCondition(CC); std::swap(TrueC, FalseC); - std::swap(TrueOp, FalseOp); } // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. @@ -14498,45 +14497,6 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, } } } - - // Handle these cases: - // (select (x != c), e, c) -> select (x != c), e, x), - // (select (x == c), c, e) -> select (x == c), x, e) - // where the c is an integer constant, and the "select" is the combination - // of CMOV and CMP. - // - // The rationale for this change is that the conditional-move from a constant - // needs two instructions, however, conditional-move from a register needs - // only one instruction. - // - // CAVEAT: By replacing a constant with a symbolic value, it may obscure - // some instruction-combining opportunities. This opt needs to be - // postponed as late as possible. - // - if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { - // the DCI.xxxx conditions are provided to postpone the optimization as - // late as possible. - - ConstantSDNode *CmpAgainst = 0; - if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) && - (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) && - dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) { - - if (CC == X86::COND_NE && - CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) { - CC = X86::GetOppositeBranchCondition(CC); - std::swap(TrueOp, FalseOp); - } - - if (CC == X86::COND_E && - CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) { - SDValue Ops[] = { FalseOp, Cond.getOperand(0), N->getOperand(2), Cond }; - return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops, - array_lengthof(Ops)); - } - } - } - return SDValue(); } diff --git a/test/CodeGen/X86/select_const.ll b/test/CodeGen/X86/select_const.ll deleted file mode 100644 index 5b2409d239..0000000000 --- a/test/CodeGen/X86/select_const.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7 | FileCheck %s - -define i64 @test1(i64 %x) nounwind { -entry: - %cmp = icmp eq i64 %x, 2 - %add = add i64 %x, 1 - %retval.0 = select i1 %cmp, i64 2, i64 %add - ret i64 %retval.0 - -; CHECK: test1: -; CHECK: leaq 1(%rdi), %rax -; CHECK: cmpq $2, %rdi -; CHECK: cmoveq %rdi, %rax -; CHECK: ret - -} |