diff options
author | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-11-08 17:20:05 +0000 |
---|---|---|
committer | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-11-08 17:20:05 +0000 |
commit | e0cb36b9fb1e1b0de9b46eafd8dc3802122b2e73 (patch) | |
tree | 57ddcdf7f61cede65612cd6ff5013ad2c11a92b1 | |
parent | 4471194d69cc99ed53dc1638e06053b069dc6454 (diff) | |
download | llvm-e0cb36b9fb1e1b0de9b46eafd8dc3802122b2e73.tar.gz llvm-e0cb36b9fb1e1b0de9b46eafd8dc3802122b2e73.tar.bz2 llvm-e0cb36b9fb1e1b0de9b46eafd8dc3802122b2e73.tar.xz |
[ARM] Implement __builtin_thread_pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/Intrinsics.td | 1 | ||||
-rw-r--r-- | include/llvm/IntrinsicsARM.td | 21 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 17 | ||||
-rw-r--r-- | test/CodeGen/ARM/thread_pointer.ll | 10 |
4 files changed, 48 insertions, 1 deletions
diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td index 9819f38952..4ede06d408 100644 --- a/include/llvm/Intrinsics.td +++ b/include/llvm/Intrinsics.td @@ -268,3 +268,4 @@ def int_init_trampoline : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, include "llvm/IntrinsicsPowerPC.td" include "llvm/IntrinsicsX86.td" +include "llvm/IntrinsicsARM.td" diff --git a/include/llvm/IntrinsicsARM.td b/include/llvm/IntrinsicsARM.td new file mode 100644 index 0000000000..1830931c1d --- /dev/null +++ b/include/llvm/IntrinsicsARM.td @@ -0,0 +1,21 @@ +//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by Lauro Ramos Venancio and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the ARM-specific intrinsics. +// +//===----------------------------------------------------------------------===// + + +//===----------------------------------------------------------------------===// +// TLS + +let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". + def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">, + Intrinsic<[llvm_ptr_ty],[IntrNoMem]>; +} diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index bc2c7c3e1e..fd2550229e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -23,6 +23,7 @@ #include "llvm/CallingConv.h" #include "llvm/Constants.h" #include "llvm/Instruction.h" +#include "llvm/Intrinsics.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -213,7 +214,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) // Turn f64->i64 into FMRRD iff target supports vfp2. setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); - + + // We want to custom lower some of our intrinsics. + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + setOperationAction(ISD::SETCC , MVT::i32, Expand); setOperationAction(ISD::SETCC , MVT::f32, Expand); setOperationAction(ISD::SETCC , MVT::f64, Expand); @@ -882,6 +886,16 @@ SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); } +static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { + MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); + switch (IntNo) { + default: return SDOperand(); // Don't custom lower most intrinsics. + case Intrinsic::arm_thread_pointer: + return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); + } +} + static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, unsigned VarArgsFrameIndex) { // vastart just stores the address of the VarArgsFrameIndex slot into the @@ -1410,6 +1424,7 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::FRAMEADDR: break; case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); } return SDOperand(); } diff --git a/test/CodeGen/ARM/thread_pointer.ll b/test/CodeGen/ARM/thread_pointer.ll new file mode 100644 index 0000000000..6476b483d7 --- /dev/null +++ b/test/CodeGen/ARM/thread_pointer.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi | \ +; RUN: grep {__aeabi_read_tp} + +define i8* @test() { +entry: + %tmp1 = call i8* @llvm.arm.thread.pointer( ) ; <i8*> [#uses=0] + ret i8* %tmp1 +} + +declare i8* @llvm.arm.thread.pointer() |