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| author | Chris Lattner <sabre@nondot.org> | 2010-07-04 22:57:10 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-07-04 22:57:10 +0000 |
| commit | e35d9842f73cb7273b1d0712183854f5f99fe24f (patch) | |
| tree | 71a9c03c4a9fd7794cb1ea7c7c2cf03d0e96d4d3 | |
| parent | 9d19989fe36e4b1b0b6449f8e54e180220b8a90a (diff) | |
| download | llvm-e35d9842f73cb7273b1d0712183854f5f99fe24f.tar.gz llvm-e35d9842f73cb7273b1d0712183854f5f99fe24f.tar.bz2 llvm-e35d9842f73cb7273b1d0712183854f5f99fe24f.tar.xz | |
fix PR7518 - terrible codegen of <2 x float>, by only marking
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 22 | ||||
| -rw-r--r-- | test/CodeGen/X86/v2f32.ll | 16 |
2 files changed, 32 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 239c42b796..f2054c9b24 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -617,7 +617,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false); addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false); addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false); - addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false); + + // FIXME: v2f32 isn't an MMX type. We currently claim that it is legal + // because of some ABI issue, but this isn't the right fix. + bool IsV2F32Legal = !Subtarget->is64Bit(); + if (IsV2F32Legal) + addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false); addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false); setOperationAction(ISD::ADD, MVT::v8i8, Legal); @@ -663,14 +668,17 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); setOperationAction(ISD::LOAD, MVT::v2i32, Promote); AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); - setOperationAction(ISD::LOAD, MVT::v2f32, Promote); - AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); + if (IsV2F32Legal) { + setOperationAction(ISD::LOAD, MVT::v2f32, Promote); + AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); + } setOperationAction(ISD::LOAD, MVT::v1i64, Legal); setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); + if (IsV2F32Legal) + setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); @@ -678,7 +686,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); + if (IsV2F32Legal) + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); @@ -697,7 +706,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom); setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom); setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom); - setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom); + if (IsV2F32Legal) + setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom); setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom); } } diff --git a/test/CodeGen/X86/v2f32.ll b/test/CodeGen/X86/v2f32.ll new file mode 100644 index 0000000000..509d528e84 --- /dev/null +++ b/test/CodeGen/X86/v2f32.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s + +; PR7518 +define void @test1(<2 x float> %Q, float *%P2) nounwind { + %a = extractelement <2 x float> %Q, i32 0 + %b = extractelement <2 x float> %Q, i32 1 + %c = fadd float %a, %b + + store float %c, float* %P2 + ret void +; CHECK: test1: +; CHECK-NEXT: addss %xmm1, %xmm0 +; CHECK-NEXT: movss %xmm0, (%rdi) +; CHECK-NEXT: ret +} + |