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| author | Mon P Wang <wangmp@apple.com> | 2010-01-23 04:35:57 +0000 |
|---|---|---|
| committer | Mon P Wang <wangmp@apple.com> | 2010-01-23 04:35:57 +0000 |
| commit | e4a0a151a5164c3dfc7bc4d6a92d57e934a88213 (patch) | |
| tree | c9bbb3ae7412ddaa4484006388897671d4689c63 | |
| parent | b2dc8f3b007a80c4b20c6c5189abf1a974c1de5e (diff) | |
| download | llvm-e4a0a151a5164c3dfc7bc4d6a92d57e934a88213.tar.gz llvm-e4a0a151a5164c3dfc7bc4d6a92d57e934a88213.tar.bz2 llvm-e4a0a151a5164c3dfc7bc4d6a92d57e934a88213.tar.xz | |
InstCombine should not fold sext/zext of a vector and a bitcast to a scalar to a sext/zext
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94280 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/VMCore/Instructions.cpp | 5 | ||||
| -rw-r--r-- | test/Transforms/InstCombine/bitcast-sext-vector.ll | 11 |
2 files changed, 14 insertions, 2 deletions
diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp index 8ff36cb6fb..e72e48cb1a 100644 --- a/lib/VMCore/Instructions.cpp +++ b/lib/VMCore/Instructions.cpp @@ -2079,8 +2079,9 @@ unsigned CastInst::isEliminableCastPair( return secondOp; case 3: // no-op cast in second op implies firstOp as long as the DestTy - // is integer - if (DstTy->isInteger()) + // is integer and we are not converting between a vector and a + // non vector type + if (SrcTy->getTypeID() != Type::VectorTyID && DstTy->isInteger()) return firstOp; return 0; case 4: diff --git a/test/Transforms/InstCombine/bitcast-sext-vector.ll b/test/Transforms/InstCombine/bitcast-sext-vector.ll new file mode 100644 index 0000000000..d70bdbaf37 --- /dev/null +++ b/test/Transforms/InstCombine/bitcast-sext-vector.ll @@ -0,0 +1,11 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +; CHECK: sext +; Don't fold zero/sign extensions with a bitcast between a vector and scalar. + +define i32 @t(<4 x i8> %src1, <4 x i8> %src2) nounwind readonly { +entry: + %cmp = icmp eq <4 x i8> %src1, %src2; <<4 x i1>> [#uses=1] + %sext = sext <4 x i1> %cmp to <4 x i8> + %val = bitcast <4 x i8> %sext to i32 + ret i32 %val +} |