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| author | Tim Northover <tnorthover@apple.com> | 2013-10-24 12:22:58 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-24 12:22:58 +0000 |
| commit | eac623a18b1e7ad9e5a7da76a323039450b7d7ce (patch) | |
| tree | abac52072a6d7a34864c6275b658ad433f7350c7 | |
| parent | ef713e27b1b9f685adc1ae35526d92c6ad0324e5 (diff) | |
| download | llvm-eac623a18b1e7ad9e5a7da76a323039450b7d7ce.tar.gz llvm-eac623a18b1e7ad9e5a7da76a323039450b7d7ce.tar.bz2 llvm-eac623a18b1e7ad9e5a7da76a323039450b7d7ce.tar.xz | |
ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.
This tidies up the obvious VFP and NEON cases I found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 12 | ||||
| -rw-r--r-- | test/MC/ARM/diagnostics-noneon.s | 7 | ||||
| -rw-r--r-- | test/MC/ARM/diagnostics.s | 17 |
4 files changed, 36 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 269c13dedb..1f7344e1c0 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5158,10 +5158,10 @@ def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0, // Vector Move Operations. // VMOV : Vector Move (Register) -def : InstAlias<"vmov${p} $Vd, $Vm", - (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; -def : InstAlias<"vmov${p} $Vd, $Vm", - (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vmov${p} $Vd, $Vm", + (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vmov${p} $Vd, $Vm", + (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; // VMOV : Vector Move (Immediate) diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index f0da06d72a..e5ddf03e48 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -671,9 +671,11 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2> { } def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), - (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>; + (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>, + Requires<[HasFPARMv8]>; def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), - (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>; + (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>, + Requires<[HasFPARMv8]>; } defm VRINTZ : vrint_inst_zrx<"z", 0, 1>; @@ -697,9 +699,11 @@ multiclass vrint_inst_anpm<string opc, bits<2> rm> { } def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), - (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>; + (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>, + Requires<[HasFPARMv8]>; def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), - (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>; + (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>, + Requires<[HasFPARMv8]>; } defm VRINTA : vrint_inst_anpm<"a", 0b00>; diff --git a/test/MC/ARM/diagnostics-noneon.s b/test/MC/ARM/diagnostics-noneon.s new file mode 100644 index 0000000000..310344ad71 --- /dev/null +++ b/test/MC/ARM/diagnostics-noneon.s @@ -0,0 +1,7 @@ +@ RUN: not llvm-mc -triple=armv7-apple-darwin -mattr=-neon < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + + vmov d5, d10 + vmov q4, q5 +@ CHECK-ERRORS: error: instruction requires: NEON +@ CHECK-ERRORS: error: instruction requires: NEON diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 4942ba06cf..35069c72a5 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -438,3 +438,20 @@ @ CHECK-ERRORS: error: writeback register not allowed in register list @ CHECK-ERRORS: error: writeback register not allowed in register list @ CHECK-ERRORS: error: writeback register not allowed in register list + + vrintz.f32.f32 s0, s1 + vrintr.f32 s0, s1 + vrintx.f64.f64 d2, d5 + vrintz.f64 d10, d9 + vrinta.f32.f32 s6, s7 + vrintn.f32 s8, s9 + vrintp.f64.f64 d10, d11 + vrintm.f64 d12, d13 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS: error: instruction requires: FPARMv8 |