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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-11 10:38:58 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-11 10:38:58 +0000 |
commit | ece929d6234b73ea248b7a5e89f915613ad748ea (patch) | |
tree | 488ff1a95c6d72e9231e2d58886f3e134cf080e9 | |
parent | 68831cbd417b7e4c47b565038a4fe9a1269d5d50 (diff) | |
download | llvm-ece929d6234b73ea248b7a5e89f915613ad748ea.tar.gz llvm-ece929d6234b73ea248b7a5e89f915613ad748ea.tar.bz2 llvm-ece929d6234b73ea248b7a5e89f915613ad748ea.tar.xz |
[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 18 | ||||
-rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 12 | ||||
-rw-r--r-- | test/CodeGen/Mips/msa/3r-d.ll | 130 |
3 files changed, 151 insertions, 9 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 1294121e58..f590cf1b17 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1225,15 +1225,15 @@ class CTCMSA_DESC { bit hasSideEffects = 1; } -class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", int_mips_div_s_b, MSA128B>; -class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", int_mips_div_s_h, MSA128H>; -class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", int_mips_div_s_w, MSA128W>; -class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", int_mips_div_s_d, MSA128D>; - -class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", int_mips_div_u_b, MSA128B>; -class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", int_mips_div_u_h, MSA128H>; -class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", int_mips_div_u_w, MSA128W>; -class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", int_mips_div_u_d, MSA128D>; +class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128B>; +class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128H>; +class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128W>; +class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128D>; + +class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128B>; +class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128H>; +class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128W>; +class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128D>; class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, MSA128H, MSA128B, MSA128B>, IsCommutable; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 0a39dda426..2de21eaffb 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -160,6 +160,8 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::STORE, Ty, Legal); setOperationAction(ISD::ADD, Ty, Legal); + setOperationAction(ISD::SDIV, Ty, Legal); + setOperationAction(ISD::UDIV, Ty, Legal); } void MipsSETargetLowering:: @@ -877,6 +879,16 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO); case Intrinsic::mips_bz_v: return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO); + case Intrinsic::mips_div_s_b: + case Intrinsic::mips_div_s_h: + case Intrinsic::mips_div_s_w: + case Intrinsic::mips_div_s_d: + return lowerMSABinaryIntr(Op, DAG, ISD::SDIV); + case Intrinsic::mips_div_u_b: + case Intrinsic::mips_div_u_h: + case Intrinsic::mips_div_u_w: + case Intrinsic::mips_div_u_d: + return lowerMSABinaryIntr(Op, DAG, ISD::UDIV); } } diff --git a/test/CodeGen/Mips/msa/3r-d.ll b/test/CodeGen/Mips/msa/3r-d.ll index 8d4d3d4e6e..ed0998dae4 100644 --- a/test/CodeGen/Mips/msa/3r-d.ll +++ b/test/CodeGen/Mips/msa/3r-d.ll @@ -91,6 +91,71 @@ declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_div_s_d_test ; + +define void @div_s_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2 + %2 = sdiv <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES + ret void +} + +; CHECK: div_s_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: div_s.b +; CHECK: st.b +; CHECK: .size div_s_b_test + +define void @div_s_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2 + %2 = sdiv <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES + ret void +} + +; CHECK: div_s_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: div_s.h +; CHECK: st.h +; CHECK: .size div_s_h_test + +define void @div_s_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2 + %2 = sdiv <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES + ret void +} + +; CHECK: div_s_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: div_s.w +; CHECK: st.w +; CHECK: .size div_s_w_test + +define void @div_s_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2 + %2 = sdiv <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES + ret void +} + +; CHECK: div_s_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: div_s.d +; CHECK: st.d +; CHECK: .size div_s_d_test +; @llvm_mips_div_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_div_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 @llvm_mips_div_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 @@ -179,6 +244,71 @@ declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_div_u_d_test ; + +define void @div_u_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2 + %2 = udiv <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES + ret void +} + +; CHECK: div_u_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: div_u.b +; CHECK: st.b +; CHECK: .size div_u_b_test + +define void @div_u_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2 + %2 = udiv <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES + ret void +} + +; CHECK: div_u_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: div_u.h +; CHECK: st.h +; CHECK: .size div_u_h_test + +define void @div_u_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2 + %2 = udiv <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES + ret void +} + +; CHECK: div_u_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: div_u.w +; CHECK: st.w +; CHECK: .size div_u_w_test + +define void @div_u_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2 + %2 = udiv <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES + ret void +} + +; CHECK: div_u_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: div_u.d +; CHECK: st.d +; CHECK: .size div_u_d_test +; @llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, |