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author | Evan Cheng <evan.cheng@apple.com> | 2007-04-17 20:23:34 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-04-17 20:23:34 +0000 |
commit | eff03db46d5d1df315cf2aa020ccd7f50ab3848e (patch) | |
tree | f1b321b4e0203420c0ff2aaad0b727d104f35508 | |
parent | 38b7ca6651643f1f98e1f7b0e7f8a3499883804b (diff) | |
download | llvm-eff03db46d5d1df315cf2aa020ccd7f50ab3848e.tar.gz llvm-eff03db46d5d1df315cf2aa020ccd7f50ab3848e.tar.bz2 llvm-eff03db46d5d1df315cf2aa020ccd7f50ab3848e.tar.xz |
Change getAllocatableSet() so it returns allocatable registers for a specific register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36215 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/Target/MRegisterInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/MRegisterInfo.cpp | 11 |
2 files changed, 11 insertions, 6 deletions
diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 23472f548d..509485ab97 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -241,8 +241,10 @@ public: } /// getAllocatableSet - Returns a bitset indexed by register number - /// indicating if a register is allocatable or not. - BitVector getAllocatableSet(MachineFunction &MF) const; + /// indicating if a register is allocatable or not. If a register class is + /// specified, returns the subset for the class. + BitVector getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC = NULL) const; const TargetRegisterDesc &operator[](unsigned RegNo) const { assert(RegNo < NumRegs && diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp index 08039208fe..ae9f20372f 100644 --- a/lib/Target/MRegisterInfo.cpp +++ b/lib/Target/MRegisterInfo.cpp @@ -34,13 +34,16 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, MRegisterInfo::~MRegisterInfo() {} -BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const { +BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC) const { BitVector Allocatable(NumRegs); for (MRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) { - const TargetRegisterClass *RC = *I; - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) + const TargetRegisterClass *TRC = *I; + if (RC && TRC != RC) + continue; + for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF), + E = TRC->allocation_order_end(MF); I != E; ++I) Allocatable.set(*I); } return Allocatable; |