summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2010-07-20 16:16:48 +0000
committerJim Grosbach <grosbach@apple.com>2010-07-20 16:16:48 +0000
commitf27ca4255290c111511d01dde54e4b4dc990dfce (patch)
treec7cd4889387fe1206b50956581c924a69b37899c
parentabff28087fd6be8150ff0e69def7de7312b2f76b (diff)
downloadllvm-f27ca4255290c111511d01dde54e4b4dc990dfce.tar.gz
llvm-f27ca4255290c111511d01dde54e4b4dc990dfce.tar.bz2
llvm-f27ca4255290c111511d01dde54e4b4dc990dfce.tar.xz
update tests for smarter BIC usage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108846 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll6
-rw-r--r--test/CodeGen/Thumb2/thumb2-and2.ll2
-rw-r--r--test/CodeGen/Thumb2/thumb2-uxtb.ll2
3 files changed, 4 insertions, 6 deletions
diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
index 3f1b9eb8d9..fb6978bb19 100644
--- a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
+++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
@@ -7,13 +7,11 @@
define void @t() nounwind ssp {
entry:
; CHECK: t:
-; CHECK: mov r0, sp
-; CHECK: bfc r0, #0, #3
+; CHECK: bic r0, sp, #7
; CHECK: subs r0, #16
; CHECK: mov sp, r0
; Yes, this is stupid codegen, but it's correct.
-; CHECK: mov r0, sp
-; CHECK: bfc r0, #0, #3
+; CHECK: bic r0, sp, #7
; CHECK: subs r0, #16
; CHECK: mov sp, r0
%size = mul i32 8, 2
diff --git a/test/CodeGen/Thumb2/thumb2-and2.ll b/test/CodeGen/Thumb2/thumb2-and2.ll
index 76c56d0047..7b0432de9b 100644
--- a/test/CodeGen/Thumb2/thumb2-and2.ll
+++ b/test/CodeGen/Thumb2/thumb2-and2.ll
@@ -30,7 +30,7 @@ define i32 @f4(i32 %a) {
ret i32 %tmp
}
; CHECK: f4:
-; CHECK: and r0, r0, #1448498774
+; CHECK: bic r0, r0, #-1448498775
; 66846720 = 0x03fc0000
define i32 @f5(i32 %a) {
diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 1fa4e5c21d..2074f98cb6 100644
--- a/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -6,7 +6,7 @@ define i32 @test1(i32 %x) {
; ARMv7A: uxtb16 r0, r0
; ARMv7M: test1
-; ARMv7M: and r0, r0, #16711935
+; ARMv7M: bic r0, r0, #-16711936
%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
ret i32 %tmp1
}