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| author | Dan Gohman <gohman@apple.com> | 2009-01-20 01:06:45 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-20 01:06:45 +0000 |
| commit | f5add58549fe8ecd9a15cbb7c230282bd693516b (patch) | |
| tree | 24b5e68ebdff5feaf033ab442492604dcb224113 | |
| parent | c2997f4a34eb544ca6ec85a5c9190feb998fc7a8 (diff) | |
| download | llvm-f5add58549fe8ecd9a15cbb7c230282bd693516b.tar.gz llvm-f5add58549fe8ecd9a15cbb7c230282bd693516b.tar.bz2 llvm-f5add58549fe8ecd9a15cbb7c230282bd693516b.tar.xz | |
Fix a dagcombine to not generate loads of non-round integer types,
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62557 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/pr3216.ll | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 0d90fc0748..6c5d386f02 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3343,7 +3343,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { // Do not generate loads of non-round integer types since these can // be expensive (and would be wrong if the type is not byte sized). - if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && + if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && // Do not change the width of a volatile load. !cast<LoadSDNode>(N0)->isVolatile()) { diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll new file mode 100644 index 0000000000..fdc814ef33 --- /dev/null +++ b/test/CodeGen/X86/pr3216.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep {sar. \$5} + +@foo = global i8 127 + +define i32 @main() nounwind { +entry: + %tmp = load i8* @foo + %bf.lo = lshr i8 %tmp, 5 + %bf.lo.cleared = and i8 %bf.lo, 7 + %0 = shl i8 %bf.lo.cleared, 5 + %bf.val.sext = ashr i8 %0, 5 + %conv = sext i8 %bf.val.sext to i32 + ret i32 %conv +} |