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| author | Tim Northover <tnorthover@apple.com> | 2014-04-15 13:59:49 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-15 13:59:49 +0000 |
| commit | 03eecdccff8d3f69412d9cbcb07c0ace7709e1e4 (patch) | |
| tree | 38c54f1ebc6af103c2098d293e947b582ba53237 /include/llvm/CodeGen/FastISel.h | |
| parent | f90c8c7063f349781a50bfb984f28af33e2b6778 (diff) | |
| download | llvm-03eecdccff8d3f69412d9cbcb07c0ace7709e1e4.tar.gz llvm-03eecdccff8d3f69412d9cbcb07c0ace7709e1e4.tar.bz2 llvm-03eecdccff8d3f69412d9cbcb07c0ace7709e1e4.tar.xz | |
FastISel: constrain the RegClass of operands when emitting instructions.
ARM64 suffered multiple -verify-machineinstr failures (principally over the
xsp/xzr issue) because FastISel was completely ignoring which subset of the
general-purpose registers each instruction required.
More fixes are coming in ARM64 specific FastISel, but this should cover the
generic problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206283 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/FastISel.h')
| -rw-r--r-- | include/llvm/CodeGen/FastISel.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index aeffbd41ca..bfeede2a34 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -343,6 +343,12 @@ protected: unsigned createResultReg(const TargetRegisterClass *RC); + /// Try to constrain Op so that it is usable by argument OpNum of the provided + /// MCInstrDesc. If this fails, create a new virtual register in the correct + /// class and COPY the value there. + unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, + unsigned OpNum); + /// Emit a constant in a register using target-specific logic, such as /// constant pool loads. virtual unsigned TargetMaterializeConstant(const Constant* C) { |