diff options
| -rw-r--r-- | lib/Target/Mips/MipsFastISel.cpp | 25 | ||||
| -rw-r--r-- | test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll | 39 |
2 files changed, 2 insertions, 62 deletions
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 9a60aa7b9f..448698e2de 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -167,14 +167,9 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr, // // more cases will be handled here in following patches. // - if (VT == MVT::i32) - EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); - else if (VT == MVT::f32) - EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset); - else if (VT == MVT::f64) - EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset); - else + if (VT != MVT::i32) return false; + EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); return true; } @@ -234,22 +229,6 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) { } unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { - int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); - if (VT == MVT::f32) { - const TargetRegisterClass *RC = &Mips::FGR32RegClass; - unsigned DestReg = createResultReg(RC); - unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass); - EmitInst(Mips::MTC1, DestReg).addReg(TempReg); - return DestReg; - } else if (VT == MVT::f64) { - const TargetRegisterClass *RC = &Mips::AFGR64RegClass; - unsigned DestReg = createResultReg(RC); - unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); - unsigned TempReg2 = - Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); - EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); - return DestReg; - } return 0; } diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll deleted file mode 100644 index 0d5906a8a1..0000000000 --- a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s - -@f = common global float 0.000000e+00, align 4 -@de = common global double 0.000000e+00, align 8 - -; Function Attrs: nounwind -define void @f1() #0 { -entry: - store float 0x3FFA76C8C0000000, float* @f, align 4 - ret void -; CHECK: .ent f1 -; CHECK: lui $[[REG1:[0-9]+]], 16339 -; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662 -; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]] -; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}}) -; CHECK: swc1 $f[[REG3]], 0($[[REG4]]) -; CHECK: .end f1 - -} - -; Function Attrs: nounwind -define void @d1() #0 { -entry: - store double 1.234567e+00, double* @de, align 8 -; CHECK: .ent d1 -; CHECK: lui $[[REG1a:[0-9]+]], 16371 -; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 -; CHECK: lui $[[REG1b:[0-9]+]], 21403 -; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 -; CHECK: mtc1 $[[REG2b]], $f[[REG3b:[0-9]+]] -; CHECK: mtc1 $[[REG2a]], $f[[REG3a:[0-9]+]] -; CHECK: sdc1 $f[[REG3b]], 0(${{[0-9]+}}) -; CHECK: .end d1 - ret void -} - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - |