diff options
Diffstat (limited to 'lib/Target/X86/X86ScheduleAtom.td')
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 56dd3407b2..87102614cc 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -22,12 +22,7 @@ def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA // SIMD/FP: SIMD ALU, FP Adder -def AtomItineraries : MultiIssueItineraries< - 2, // IssueWidth=2 allows 2 instructions per scheduling group. - 1, // MinLatency=1. InstrStage cycles overrides MinLatency. - // OperandCycles may be used for expected latency. - 3, // LoadLatency (expected, may be overriden by OperandCycles) - 30,// HighLatency (expected, may be overriden by OperandCycles) +def AtomItineraries : ProcessorItineraries< [ Port0, Port1 ], [], [ // P0 only @@ -523,3 +518,13 @@ def AtomItineraries : MultiIssueItineraries< InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] > ]>; +// Atom machine model. +def AtomModel : SchedMachineModel { + let IssueWidth = 2; // Allows 2 instructions per scheduling group. + let MinLatency = 1; // InstrStage cycles overrides MinLatency. + // OperandCycles may be used for expected latency. + let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles. + let HighLatency = 30;// Expected, may be overriden by OperandCycles. + + let Itineraries = AtomItineraries; +} |