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authorSilviu Baranga <silviu.baranga@arm.com>2013-10-21 10:54:53 +0000
committerSilviu Baranga <silviu.baranga@arm.com>2013-10-21 10:54:53 +0000
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Add the __ARM_ARCH_EXT_IDIV__ predefine. It is set to 1 if we have hardware divide in the mode that we are compiling in (depending on the target features), not defined if we don't. Should be compatible with the GCC conterpart. Also adding a -hwdiv option to overide the default behavior.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@193074 91177308-0d34-0410-b5e6-96231b3b80d8
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diff --git a/docs/UsersManual.rst b/docs/UsersManual.rst
index 50908ad1cb..68fd0283ad 100644
--- a/docs/UsersManual.rst
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@@ -1047,6 +1047,17 @@ are listed below.
efficient model can be used. The TLS model can be overridden per
variable using the ``tls_model`` attribute.
+.. option:: -mhwdiv=[values]
+
+ Select the ARM modes (arm or thumb) that support hardware division
+ instructions.
+
+ Valid values are: ``arm``, ``thumb`` and ``arm,thumb``.
+ This option is used to indicate which mode (arm or thumb) supports
+ hardware division instructions. This only applies to the ARM
+ architecture.
+
+
Controlling Size of Debug Information
-------------------------------------