Introduce arm_acle.h supporting existing LLVM builtin intrinsics

Summary: This patch introduces ACLE header file, implementing extensions that can be directly mapped to existing Clang intrinsics. It implements for both AArch32 and AArch64.

Reviewers: t.p.northover, compnerd, rengolin

Reviewed By: compnerd, rengolin

Subscribers: rnk, echristo, compnerd, aemerson, mroth, cfe-commits

Differential Revision: http://reviews.llvm.org/D4296

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@211962 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 152 insertions, 0 deletions

diff --git a/test/CodeGen/arm_acle.c b/test/CodeGen/arm_acle.c
new file mode 100644
index 0000000000..17462e8ae4
--- /dev/null
+++ b/test/CodeGen/arm_acle.c
@@ -0,0 +1,129 @@
+// RUN: %clang_cc1 -triple armv8 -target-cpu cortex-a57 -O -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch32
+// RUN: %clang_cc1 -triple aarch64 -target-cpu cortex-a57 -O -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch64
+
+#include <arm_acle.h>
+#include <stdint.h>
+
+/* Miscellaneous data-processing intrinsics */
+// ARM-LABEL: test_rev
+// ARM: call i32 @llvm.bswap.i32(i32 %t)
+uint32_t test_rev(uint32_t t) {
+  return __rev(t);
+}
+
+// ARM-LABEL: test_revl
+// AArch32: call i32 @llvm.bswap.i32(i32 %t)
+// AArch64: call i64 @llvm.bswap.i64(i64 %t)
+long test_revl(long t) {
+  return __revl(t);
+}
+
+// ARM-LABEL: test_revll
+// ARM: call i64 @llvm.bswap.i64(i64 %t)
+uint64_t test_revll(uint64_t t) {
+  return __revll(t);
+}
+
+// ARM-LABEL: test_clz
+// ARM: call i32 @llvm.ctlz.i32(i32 %t, i1 false)
+uint32_t test_clz(uint32_t t) {
+  return __clz(t);
+}
+
+// ARM-LABEL: test_clzl
+// AArch32: call i32 @llvm.ctlz.i32(i32 %t, i1 false)
+// AArch64: call i64 @llvm.ctlz.i64(i64 %t, i1 false)
+long test_clzl(long t) {
+  return __clzl(t);
+}
+
+// ARM-LABEL: test_clzll
+// ARM: call i64 @llvm.ctlz.i64(i64 %t, i1 false)
+uint64_t test_clzll(uint64_t t) {
+  return __clzll(t);
+}
+
+/* Saturating intrinsics */
+#ifdef __ARM_32BIT_STATE
+// AArch32-LABEL: test_ssat
+// AArch32: call i32 @llvm.arm.ssat(i32 %t, i32 1)
+int32_t test_ssat(int32_t t) {
+  return __ssat(t, 1);
+}
+
+// AArch32-LABEL: test_usat
+// AArch32: call i32 @llvm.arm.usat(i32 %t, i32 2)
+int32_t test_usat(int32_t t) {
+  return __usat(t, 2);
+}
+// AArch32-LABEL: test_qadd
+// AArch32: call i32 @llvm.arm.qadd(i32 %a, i32 %b)
+int32_t test_qadd(int32_t a, int32_t b) {
+  return __qadd(a, b);
+}
+
+// AArch32-LABEL: test_qsub
+// AArch32: call i32 @llvm.arm.qsub(i32 %a, i32 %b)
+int32_t test_qsub(int32_t a, int32_t b) {
+  return __qsub(a, b);
+}
+#endif
+
+/* CRC32 intrinsics */
+// ARM-LABEL: test_crc32b
+// AArch32: call i32 @llvm.arm.crc32b
+// AArch64: call i32 @llvm.aarch64.crc32b
+uint32_t test_crc32b(uint32_t a, uint8_t b) {
+  return __crc32b(a, b);
+}
+
+// ARM-LABEL: test_crc32h
+// AArch32: call i32 @llvm.arm.crc32h
+// AArch64: call i32 @llvm.aarch64.crc32h
+uint32_t test_crc32h(uint32_t a, uint16_t b) {
+  return __crc32h(a, b);
+}
+
+// ARM-LABEL: test_crc32w
+// AArch32: call i32 @llvm.arm.crc32w
+// AArch64: call i32 @llvm.aarch64.crc32w
+uint32_t test_crc32w(uint32_t a, uint32_t b) {
+  return __crc32w(a, b);
+}
+
+// ARM-LABEL: test_crc32d
+// AArch32: call i32 @llvm.arm.crc32w
+// AArch32: call i32 @llvm.arm.crc32w
+// AArch64: call i32 @llvm.aarch64.crc32x
+uint32_t test_crc32d(uint32_t a, uint64_t b) {
+  return __crc32d(a, b);
+}
+
+// ARM-LABEL: test_crc32cb
+// AArch32: call i32 @llvm.arm.crc32cb
+// AArch64: call i32 @llvm.aarch64.crc32cb
+uint32_t test_crc32cb(uint32_t a, uint8_t b) {
+  return __crc32cb(a, b);
+}
+
+// ARM-LABEL: test_crc32ch
+// AArch32: call i32 @llvm.arm.crc32ch
+// AArch64: call i32 @llvm.aarch64.crc32ch
+uint32_t test_crc32ch(uint32_t a, uint16_t b) {
+  return __crc32ch(a, b);
+}
+
+// ARM-LABEL: test_crc32cw
+// AArch32: call i32 @llvm.arm.crc32cw
+// AArch64: call i32 @llvm.aarch64.crc32cw
+uint32_t test_crc32cw(uint32_t a, uint32_t b) {
+  return __crc32cw(a, b);
+}
+
+// ARM-LABEL: test_crc32cd
+// AArch32: call i32 @llvm.arm.crc32cw
+// AArch32: call i32 @llvm.arm.crc32cw
+// AArch64: call i32 @llvm.aarch64.crc32cx
+uint32_t test_crc32cd(uint32_t a, uint64_t b) {
+  return __crc32cd(a, b);
+}
diff --git a/test/Headers/arm-acle-header.c b/test/Headers/arm-acle-header.c
new file mode 100644
index 0000000000..523e77e486
--- /dev/null
+++ b/test/Headers/arm-acle-header.c
@@ -0,0 +1,7 @@
+// RUN: %clang_cc1 -triple armv7 -target-cpu cortex-a15 -fsyntax-only -ffreestanding %s
+// RUN: %clang_cc1 -triple aarch64 -target-cpu cortex-a53 -fsyntax-only -ffreestanding %s
+// RUN: %clang_cc1 -x c++ -triple armv7 -target-cpu cortex-a15 -fsyntax-only -ffreestanding %s
+// RUN: %clang_cc1 -x c++ -triple aarch64 -target-cpu cortex-a57 -fsyntax-only -ffreestanding %s
+// expected-no-diagnostics
+
+#include <arm_acle.h>
diff --git a/test/Sema/arm_acle.c b/test/Sema/arm_acle.c
new file mode 100644
index 0000000000..0bdbdce2a9
--- /dev/null
+++ b/test/Sema/arm_acle.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple armv8 -target-cpu cortex-a57 -fsyntax-only -verify %s
+
+#include <arm_acle.h>
+
+/*
+ * Saturating intrinsics
+ * Second argument for SSAT and USAT intrinsics must be compile-time constant,
+ * otherwise an error should be raised.
+ */
+int32_t test_ssat_const_diag(int32_t t, const int32_t v) {
+  return __ssat(t, v);  // expected-error-re {{argument to {{.*}} must be a constant integer}}
+}
+
+int32_t test_usat_const_diag(int32_t t, const int32_t v) {
+  return __usat(t, v);  // expected-error-re {{argument to {{.*}} must be a constant integer}}
+}