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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-28 18:14:21 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-01-28 18:14:21 +0000 |
| commit | 106b79744b185969faf8a74c6bd7cad35e6f11bd (patch) | |
| tree | 4c15347510f68dd40e18caff39499634243557a1 /.arcconfig | |
| parent | bb6f2367296bf6e78049ff32e7fa4f7c96d80a47 (diff) | |
| download | llvm-106b79744b185969faf8a74c6bd7cad35e6f11bd.tar.gz llvm-106b79744b185969faf8a74c6bd7cad35e6f11bd.tar.bz2 llvm-106b79744b185969faf8a74c6bd7cad35e6f11bd.tar.xz | |
[X86] Add extra rules for combining vselect dag nodes into movsd.
This improves the fix committed at revision 199683 adding the
following new target specific combine rules:
1) fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
(v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) ))
2) fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
(v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) ))
3) fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
(v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))
4) fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
(v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200324 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to '.arcconfig')
0 files changed, 0 insertions, 0 deletions