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author | Evan Cheng <evan.cheng@apple.com> | 2010-05-19 20:19:50 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-19 20:19:50 +0000 |
commit | 211ffa13519cadfb7f9baf4c8447fa055bf38fe8 (patch) | |
tree | bc37d5def2f4871b5a41e236e6c4f670db1fe2f5 | |
parent | 343735288798bbd1cd2ed2750fa6cd323f12c26c (diff) | |
download | llvm-211ffa13519cadfb7f9baf4c8447fa055bf38fe8.tar.gz llvm-211ffa13519cadfb7f9baf4c8447fa055bf38fe8.tar.bz2 llvm-211ffa13519cadfb7f9baf4c8447fa055bf38fe8.tar.xz |
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 11 | ||||
-rw-r--r-- | include/llvm/Target/TargetMachine.h | 7 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/MSP430/MSP430ISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 2 |
10 files changed, 20 insertions, 18 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index f681259c34..b06a7b9304 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -97,11 +97,6 @@ public: ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. }; - enum SchedPreference { - SchedulingForLatency, // Scheduling for shortest total latency. - SchedulingForRegPressure // Scheduling for lowest register pressure. - }; - /// NOTE: The constructor takes ownership of TLOF. explicit TargetLowering(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF); @@ -150,7 +145,7 @@ public: BooleanContent getBooleanContents() const { return BooleanContents;} /// getSchedulingPreference - Return target scheduling preference. - SchedPreference getSchedulingPreference() const { + Sched::Preference getSchedulingPreference() const { return SchedPreferenceInfo; } @@ -906,7 +901,7 @@ protected: void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } /// setSchedulingPreference - Specify the target scheduling preference. - void setSchedulingPreference(SchedPreference Pref) { + void setSchedulingPreference(Sched::Preference Pref) { SchedPreferenceInfo = Pref; } @@ -1521,7 +1516,7 @@ private: /// SchedPreferenceInfo - The target scheduling preference: shortest possible /// total cycles or lowest register usage. - SchedPreference SchedPreferenceInfo; + Sched::Preference SchedPreferenceInfo; /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers unsigned JumpBufSize; diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 580998f2bf..aa7a30a759 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -70,6 +70,13 @@ namespace CodeGenOpt { }; } +namespace Sched { + enum Preference { + Latency, // Scheduling for shortest total latency. + RegPressure // Scheduling for lowest register pressure. + }; +} + //===----------------------------------------------------------------------===// /// /// TargetMachine - Primary interface to the complete machine description for diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 5988688eed..76e09e79f9 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -132,10 +132,10 @@ namespace llvm { if (OptLevel == CodeGenOpt::None) return createFastDAGScheduler(IS, OptLevel); - if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) + if (TLI.getSchedulingPreference() == Sched::Latency) return createTDListDAGScheduler(IS, OptLevel); - assert(TLI.getSchedulingPreference() == - TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); + assert(TLI.getSchedulingPreference() == Sched::RegPressure && + "Unknown sched type!"); return createBURRListDAGScheduler(IS, OptLevel); } } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 94a5757264..44a80d3362 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -543,7 +543,7 @@ TargetLowering::TargetLowering(const TargetMachine &tm, ExceptionPointerRegister = 0; ExceptionSelectorRegister = 0; BooleanContents = UndefinedBooleanContent; - SchedPreferenceInfo = SchedulingForLatency; + SchedPreferenceInfo = Sched::Latency; JumpBufSize = 0; JumpBufAlignment = 0; IfCvtBlockSizeLimit = 2; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f5373cb0e7..62852b1768 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -466,7 +466,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setTargetDAGCombine(ISD::MUL); setStackPointerRegisterToSaveRestore(ARM::SP); - setSchedulingPreference(SchedulingForRegPressure); + setSchedulingPreference(Sched::RegPressure); // FIXME: If-converter should use instruction latency to determine // profitability rather than relying on fixed limits. diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 5e04454f6a..081e8d0db0 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -485,7 +485,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) // Set pre-RA register scheduler default to BURR, which produces slightly // better code than the default (could also be TDRR, but TargetLowering.h // needs a mod to support that model): - setSchedulingPreference(SchedulingForRegPressure); + setSchedulingPreference(Sched::RegPressure); } const char * diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index c3e2bdf7b4..51565bb80a 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -83,7 +83,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : setStackPointerRegisterToSaveRestore(MSP430::SPW); setBooleanContents(ZeroOrOneBooleanContent); - setSchedulingPreference(SchedulingForLatency); + setSchedulingPreference(Sched::Latency); // We have post-incremented loads / stores. setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index e98f18b9a3..76f29010d0 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -81,7 +81,7 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : // LLVM's current latency-oriented scheduler can't handle physreg definitions // such as SystemZ has with PSW, so set this to the register-pressure // scheduler, because it can. - setSchedulingPreference(SchedulingForRegPressure); + setSchedulingPreference(Sched::RegPressure); setBooleanContents(ZeroOrOneBooleanContent); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9fa7bb1d3c..4206cbb2ee 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -94,7 +94,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // X86 is weird, it always uses i8 for shift amounts and setcc results. setShiftAmountType(MVT::i8); setBooleanContents(ZeroOrOneBooleanContent); - setSchedulingPreference(SchedulingForRegPressure); + setSchedulingPreference(Sched::RegPressure); setStackPointerRegisterToSaveRestore(X86StackPtr); if (Subtarget->isTargetDarwin()) { diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 3990b8b3c0..b23057226c 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -80,7 +80,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) setShiftAmountType(MVT::i32); setStackPointerRegisterToSaveRestore(XCore::SP); - setSchedulingPreference(SchedulingForRegPressure); + setSchedulingPreference(Sched::RegPressure); // Use i32 for setcc operations results (slt, sgt, ...). setBooleanContents(ZeroOrOneBooleanContent); |