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author | Evan Cheng <evan.cheng@apple.com> | 2009-06-30 09:19:42 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-30 09:19:42 +0000 |
commit | 50564ebc9e3d7ff806062023e6511e91065df0d2 (patch) | |
tree | 44d13435740f60f53f9b19e09aebfbd3f9ff0f9e | |
parent | 4784f1fc73abf6005b7b7262d395af71b57b1255 (diff) | |
download | llvm-50564ebc9e3d7ff806062023e6511e91065df0d2.tar.gz llvm-50564ebc9e3d7ff806062023e6511e91065df0d2.tar.bz2 llvm-50564ebc9e3d7ff806062023e6511e91065df0d2.tar.xz |
Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/CodeGen/RegisterScavenging.h | 15 | ||||
-rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 28 | ||||
-rw-r--r-- | test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll | 116 |
3 files changed, 152 insertions, 7 deletions
diff --git a/include/llvm/CodeGen/RegisterScavenging.h b/include/llvm/CodeGen/RegisterScavenging.h index 458c2e4487..a4ed0129eb 100644 --- a/include/llvm/CodeGen/RegisterScavenging.h +++ b/include/llvm/CodeGen/RegisterScavenging.h @@ -69,6 +69,10 @@ class RegScavenger { /// available, unset means the register is currently being used. BitVector RegsAvailable; + /// ImplicitDefed - If bit is set that means the register is defined by an + /// implicit_def instructions. That means it can be clobbered at will. + BitVector ImplicitDefed; + /// CurrDist - Distance from MBB entry to the current instruction MBBI. /// unsigned CurrDist; @@ -113,18 +117,25 @@ public: bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; } bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; } + bool isImplicitlyDefined(unsigned Reg) const { return ImplicitDefed[Reg]; } + /// getRegsUsed - return all registers currently in use in used. void getRegsUsed(BitVector &used, bool includeReserved); /// setUsed / setUnused - Mark the state of one or a number of registers. /// - void setUsed(unsigned Reg); - void setUsed(BitVector &Regs) { + void setUsed(unsigned Reg, bool ImpDef = false); + void setUsed(BitVector &Regs, bool ImpDef = false) { RegsAvailable &= ~Regs; + if (ImpDef) + ImplicitDefed |= Regs; + else + ImplicitDefed &= ~Regs; } void setUnused(unsigned Reg, const MachineInstr *MI); void setUnused(BitVector &Regs) { RegsAvailable |= Regs; + ImplicitDefed &= ~Regs; } /// FindUnusedReg - Find a unused register of the specified register class diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 7d8e3afa78..382741ee73 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -57,22 +57,28 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI, } /// setUsed - Set the register and its sub-registers as being used. -void RegScavenger::setUsed(unsigned Reg) { +void RegScavenger::setUsed(unsigned Reg, bool ImpDef) { RegsAvailable.reset(Reg); + ImplicitDefed[Reg] = ImpDef; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - unsigned SubReg = *SubRegs; ++SubRegs) + unsigned SubReg = *SubRegs; ++SubRegs) { RegsAvailable.reset(SubReg); + ImplicitDefed[SubReg] = ImpDef; + } } /// setUnused - Set the register and its sub-registers as being unused. void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) { RegsAvailable.set(Reg); + ImplicitDefed.reset(Reg); for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) - if (!RedefinesSuperRegPart(MI, Reg, TRI)) + if (!RedefinesSuperRegPart(MI, Reg, TRI)) { RegsAvailable.set(SubReg); + ImplicitDefed.reset(SubReg); + } } void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { @@ -88,6 +94,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { if (!MBB) { NumPhysRegs = TRI->getNumRegs(); RegsAvailable.resize(NumPhysRegs); + ImplicitDefed.resize(NumPhysRegs); // Create reserved registers bitvector. ReservedRegs = TRI->getReservedRegs(MF); @@ -106,6 +113,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { ScavengeRestore = NULL; CurrDist = 0; DistanceMap.clear(); + ImplicitDefed.reset(); // All registers started out unused. RegsAvailable.set(); @@ -187,6 +195,8 @@ void RegScavenger::forward() { ScavengeRestore = NULL; } + bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF; + // Separate register operands into 3 classes: uses, defs, earlyclobbers. SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs; @@ -211,7 +221,14 @@ void RegScavenger::forward() { assert(isUsed(Reg) && "Using an undefined register!"); - if (MO.isKill() && !isReserved(Reg)) { + // Kill of implicit_def defined registers are ignored. e.g. + // entry: 0x2029ab8, LLVM BB @0x1b06080, ID#0: + // Live Ins: %R0 + // %R0<def> = IMPLICIT_DEF + // %R0<def> = IMPLICIT_DEF + // STR %R0<kill>, %R0, %reg0, 0, 14, %reg0, Mem:ST(4,4) [0x1b06510 + 0] + // %R1<def> = LDR %R0, %reg0, 24, 14, %reg0, Mem:LD(4,4) [0x1b065bc + 0] + if (MO.isKill() && !isReserved(Reg) && !isImplicitlyDefined(Reg)) { KillRegs.set(Reg); // Mark sub-registers as used. @@ -257,9 +274,10 @@ void RegScavenger::forward() { // Implicit def is allowed to "re-define" any register. Similarly, // implicitly defined registers can be clobbered. assert((isReserved(Reg) || isUnused(Reg) || + IsImpDef || isImplicitlyDefined(Reg) || isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && "Re-defining a live register!"); - setUsed(Reg); + setUsed(Reg, IsImpDef); } } diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll new file mode 100644 index 0000000000..3a14d67247 --- /dev/null +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -0,0 +1,116 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@no_mat = external global i32 ; <i32*> [#uses=1] +@no_mis = external global i32 ; <i32*> [#uses=2] +@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] +@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] +@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] + +declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind + +declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + %0 = load i32* undef, align 4 ; <i32> [#uses=3] + %1 = add i32 %0, 1 ; <i32> [#uses=2] + store i32 %1, i32* undef, align 4 + %2 = load i32* undef, align 4 ; <i32> [#uses=2] + %3 = sub i32 %2, %0 ; <i32> [#uses=1] + store i32 0, i32* @no_mat, align 4 + store i32 0, i32* @no_mis, align 4 + %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] + tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] + %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1] + %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] + %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + br i1 undef, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + br i1 undef, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + br i1 undef, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + br i1 undef, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + br i1 undef, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + %indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; <i32> [#uses=2] + %tmp13 = add i32 %indvar11, 1 ; <i32> [#uses=2] + %count.0 = sub i32 undef, %indvar11 ; <i32> [#uses=0] + br i1 undef, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} |