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author | Derek Schuff <dschuff@google.com> | 2013-05-15 16:08:30 +0000 |
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committer | Derek Schuff <dschuff@google.com> | 2013-05-15 16:08:30 +0000 |
commit | 6fc631978cdd1128a790854e497e267639d9325d (patch) | |
tree | 38eab3a8881f6092dcef6520ad57096c6c2a2186 | |
parent | db3cc56e7018f6a553ba6bea8aeb6ee32aa121d8 (diff) | |
download | llvm-6fc631978cdd1128a790854e497e267639d9325d.tar.gz llvm-6fc631978cdd1128a790854e497e267639d9325d.tar.bz2 llvm-6fc631978cdd1128a790854e497e267639d9325d.tar.xz |
Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for
v6+ Darwin as well as for v7+ on other targets.
The distinction is made because v6 doesn't guarantee support (but LLVM assumes
that Apple controls hardware+kernel and therefore have conformant v6 CPUs),
whereas v7 does provide this guarantee (and Linux behaves sanely).
Overall this should slightly improve performance in most cases because of
reduced I$ pressure.
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181897 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 8653c462f0..9ff0d61481 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -162,10 +162,23 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { if (!isThumb() || hasThumb2()) PostRAScheduler = true; - // v6+ may or may not support unaligned mem access depending on the system - // configuration. - if (!StrictAlign && hasV6Ops() && isTargetDarwin()) - AllowsUnalignedMem = true; + if (!StrictAlign) { + // Assume pre-ARMv6 doesn't support unaligned accesses. + // + // ARMv6 may or may not support unaligned accesses depending on the + // SCTLR.U bit, which is architecture-specific. We assume ARMv6 + // Darwin targets support unaligned accesses, and others don't. + // + // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit + // which raises an alignment fault on unaligned accesses. Linux + // defaults this bit to 0 and handles it as a system-wide (not + // per-process) setting. It is therefore safe to assume that ARMv7+ + // targets support unaligned accesses. + // + // The above behavior is consistent with GCC. + if (hasV7Ops() || (hasV6Ops() && isTargetDarwin())) + AllowsUnalignedMem = true; + } // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default. uint64_t Bits = getFeatureBits(); |