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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2013-01-08 18:02:19 -0600
committerAbdoulaye Walsimou Gaye <awg@embtoolkit.org>2013-01-13 12:27:30 +0100
commit19e7d419f9d3b5cc9333b58859d9e215c8c40150 (patch)
tree0672cfcca59b4974422bd11428c94af048039111
parentab38b966e20ecfc5ea0fd6ea1576eb8925071a62 (diff)
downloadllvm-embtoolkit-1.1.0.tar.gz
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llvm-embtoolkit-1.1.0.tar.xz
Properly recognize "memory" constraint in clobber list of inline asm.embtoolkit-1.1.0
Signed-off-by: Abdoulaye Walsimou Gaye <awg@embtoolkit.org>
-rw-r--r--lib/CodeGen/MachineInstr.cpp6
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp6
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp10
-rw-r--r--test/CodeGen/Generic/inline-asm-mem-clobber.ll21
4 files changed, 39 insertions, 4 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index ce8d52000b..4a6a484af4 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -1545,10 +1545,14 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
OS << " ";
getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
- // Print HasSideEffects, IsAlignStack
+ // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
OS << " [sideeffect]";
+ if (ExtraInfo & InlineAsm::Extra_MayLoad)
+ OS << " [mayload]";
+ if (ExtraInfo & InlineAsm::Extra_MayStore)
+ OS << " [maystore]";
if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
OS << " [alignstack]";
if (getInlineAsmDialect() == InlineAsm::AD_ATT)
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 3fbf7c2fe6..b055696b90 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6052,6 +6052,10 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// Compute the constraint code and ConstraintType to use.
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
+ if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
+ OpInfo.Type == InlineAsm::isClobber)
+ continue;
+
// If this is a memory input, and if the operand is not indirect, do what we
// need to to provide an address for the memory input.
if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
@@ -6155,6 +6159,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
ExtraInfo |= InlineAsm::Extra_MayLoad;
else if (OpInfo.Type == InlineAsm::isOutput)
ExtraInfo |= InlineAsm::Extra_MayStore;
+ else if (OpInfo.Type == InlineAsm::isClobber)
+ ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
}
}
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 49f55e2fc6..f6b887d6e9 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2707,7 +2707,9 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
TargetLowering::ConstraintType
TargetLowering::getConstraintType(const std::string &Constraint) const {
- if (Constraint.size() == 1) {
+ unsigned S = Constraint.size();
+
+ if (S == 1) {
switch (Constraint[0]) {
default: break;
case 'r': return C_RegisterClass;
@@ -2736,9 +2738,11 @@ TargetLowering::getConstraintType(const std::string &Constraint) const {
}
}
- if (Constraint.size() > 1 && Constraint[0] == '{' &&
- Constraint[Constraint.size()-1] == '}')
+ if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
+ if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
+ return C_Memory;
return C_Register;
+ }
return C_Unknown;
}
diff --git a/test/CodeGen/Generic/inline-asm-mem-clobber.ll b/test/CodeGen/Generic/inline-asm-mem-clobber.ll
new file mode 100644
index 0000000000..e523d031dc
--- /dev/null
+++ b/test/CodeGen/Generic/inline-asm-mem-clobber.ll
@@ -0,0 +1,21 @@
+; RUN: llc -O2 < %s | FileCheck %s
+
+@G = common global i32 0, align 4
+
+define i32 @foo(i8* %p) nounwind uwtable {
+entry:
+ %p.addr = alloca i8*, align 8
+ %rv = alloca i32, align 4
+ store i8* %p, i8** %p.addr, align 8
+ store i32 0, i32* @G, align 4
+ %0 = load i8** %p.addr, align 8
+; CHECK: blah
+ %1 = call i32 asm "blah", "=r,r,~{memory}"(i8* %0) nounwind
+; CHECK: @G
+ store i32 %1, i32* %rv, align 4
+ %2 = load i32* %rv, align 4
+ %3 = load i32* @G, align 4
+ %add = add nsw i32 %2, %3
+ ret i32 %add
+}
+