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author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2011-12-28 08:14:01 +0000 |
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committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2011-12-28 08:14:01 +0000 |
commit | 021c0a2ee7121c4ccd0765699c14f8c9f7f7c596 (patch) | |
tree | 08d392eaebed03037c207ad8531c4b1f880df2c3 | |
parent | 8da7ddf2d28d27e8b7fd8b7f159e2d9584bdc819 (diff) | |
download | llvm-021c0a2ee7121c4ccd0765699c14f8c9f7f7c596.tar.gz llvm-021c0a2ee7121c4ccd0765699c14f8c9f7f7c596.tar.bz2 llvm-021c0a2ee7121c4ccd0765699c14f8c9f7f7c596.tar.xz |
Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 29 | ||||
-rw-r--r-- | test/CodeGen/X86/avx-shuffle.ll | 16 |
2 files changed, 40 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 16a3d090e9..00b46d2cf6 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3448,6 +3448,11 @@ bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { + EVT VT = N->getValueType(0); + + if (VT.getSizeInBits() != 128) + return false; + unsigned NumElems = N->getValueType(0).getVectorNumElements(); if (NumElems != 2 && NumElems != 4) @@ -3666,6 +3671,8 @@ bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { if (VT.getVectorElementType().getSizeInBits() < 32) return false; + if (VT.getSizeInBits() == 256) + return false; int NumElts = VT.getVectorNumElements(); @@ -5158,16 +5165,30 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || (ExtVT == MVT::i64 && Subtarget->is64Bit())) { + if (VT.getSizeInBits() == 256) { + + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), + DAG, dl); + } Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), DAG); } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); - unsigned NumBits = VT.getSizeInBits(); - assert((NumBits == 128 || NumBits == 256) && - "Expected an SSE or AVX value type!"); - EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32; + if (VT.getSizeInBits() == 256) { + + EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); + Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); + SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); + return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), + DAG, dl); + } + assert (VT.getSizeInBits() == 128 || "Expected an SSE value type!"); + EVT MiddleVT = MVT::v4i32; Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasXMMInt(), DAG); diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll index e9392ae607..8532b40613 100644 --- a/test/CodeGen/X86/avx-shuffle.ll +++ b/test/CodeGen/X86/avx-shuffle.ll @@ -13,8 +13,22 @@ define <4 x float> @test1(<4 x float> %a) nounwind { define <3 x i64> @test2(<2 x i64> %v) nounwind readnone { ; CHECK: test2: ; CHECK: vxorpd -; CHECK: vmovsd +; CHECK: vperm2f128 %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef> %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2> ret <3 x i64> %2 } + +define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind { + %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef> + ret <4 x i64> %c +; CHECK: test3: +; CHECK: vperm2f128 +} + +define <8 x float> @test4(float %a) nounwind { + %b = insertelement <8 x float> zeroinitializer, float %a, i32 0 + ret <8 x float> %b +; CHECK: test4: +; CHECK: vinsertf128 +}
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