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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-02-07 19:48:00 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-02-07 19:48:00 +0000 |
commit | 0c66403efdf88ff4f247b6a9f45339bb3a893235 (patch) | |
tree | 7cec1e1f88759a2601ab41f7a0636a673e5c7a58 | |
parent | 184f5c1545e06a99951f14d846a1d853ff19a2b8 (diff) | |
download | llvm-0c66403efdf88ff4f247b6a9f45339bb3a893235.tar.gz llvm-0c66403efdf88ff4f247b6a9f45339bb3a893235.tar.bz2 llvm-0c66403efdf88ff4f247b6a9f45339bb3a893235.tar.xz |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 3 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 3 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 11 | ||||
-rw-r--r-- | test/MC/Mips/mips-jump-instructions.s | 8 |
4 files changed, 22 insertions, 3 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index db92c64c05..494ba87b40 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -170,6 +170,7 @@ def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; } let DecoderNamespace = "Mips64" in def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; +def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>; def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; let DecoderNamespace = "Mips64" in { @@ -329,6 +330,8 @@ def : InstAlias<"not $rt, $rs", (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, Requires<[HasMips64]>; def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; +def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>, + Requires<[HasMips64]>; def : InstAlias<"daddu $rs, $rt, $imm", (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 1>; diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 6977e45264..ee432c8753 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -367,6 +367,7 @@ class LUI_FM { } class JALR_FM { + bits<5> rd; bits<5> rs; bits<32> Inst; @@ -374,7 +375,7 @@ class JALR_FM { let Inst{31-26} = 0; let Inst{25-21} = rs; let Inst{20-16} = 0; - let Inst{15-11} = 31; + let Inst{15-11} = rd; let Inst{10-6} = 0; let Inst{5-0} = 9; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 7e33cb1846..c85b547d0e 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -565,9 +565,14 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in { let DecoderMethod = "DecodeJumpTarget"; } + class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, + Register RetReg>: + PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, + PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; + class JumpLinkReg<string opstr, RegisterClass RC>: - InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), - [(MipsJmpLink RC:$rs)], IIBranch, FrmR>; + InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), + [], IIBranch, FrmR>; class BGEZAL_FT<string opstr, RegisterOperand RO> : InstSE<(outs), (ins RO:$rs, brtarget:$offset), @@ -865,6 +870,7 @@ def BAL_BR: BAL_FT, BAL_FM; def JAL : JumpLink<"jal">, FJ<3>; def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; +def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; @@ -972,6 +978,7 @@ def : InstAlias<"and $rs, $rt, $imm", (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, Requires<[NotMips64]>; +def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; def : InstAlias<"not $rt, $rs", (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; def : InstAlias<"neg $rt, $rs", diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s index 58250f306e..bc2d720398 100644 --- a/test/MC/Mips/mips-jump-instructions.s +++ b/test/MC/Mips/mips-jump-instructions.s @@ -56,6 +56,10 @@ end_of_code: # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00] # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00] # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00] @@ -67,6 +71,10 @@ end_of_code: nop jalr $6 nop + jalr $31, $25 + nop + jalr $10, $11 + nop jr $7 nop j $7 |