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author | Cameron Zwarich <zwarich@apple.com> | 2011-04-15 21:24:38 +0000 |
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committer | Cameron Zwarich <zwarich@apple.com> | 2011-04-15 21:24:38 +0000 |
commit | 0cb11ac32fc09c5db42fb801db242ac9fb51f6b1 (patch) | |
tree | 9ab277597e35edd12827665a3179cdd1b21e595f | |
parent | 3e03e5d2a95670efec327550d15895c25e7fc43b (diff) | |
download | llvm-0cb11ac32fc09c5db42fb801db242ac9fb51f6b1.tar.gz llvm-0cb11ac32fc09c5db42fb801db242ac9fb51f6b1.tar.bz2 llvm-0cb11ac32fc09c5db42fb801db242ac9fb51f6b1.tar.xz |
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
a case involving EOR, so I only added a test for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 | ||||
-rw-r--r-- | test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll | 25 |
2 files changed, 31 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 465d6122aa..0789279133 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1642,7 +1642,15 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask, case ARM::ANDrr: case ARM::ANDri: case ARM::t2ANDrr: - case ARM::t2ANDri: { + case ARM::t2ANDri: + case ARM::ORRrr: + case ARM::ORRri: + case ARM::t2ORRrr: + case ARM::t2ORRri: + case ARM::EORrr: + case ARM::EORri: + case ARM::t2EORrr: + case ARM::t2EORri: { // Scan forward for the use of CPSR, if it's a conditional code requires // checking of V bit, then this is not safe to do. If we can't find the // CPSR use (i.e. used in another block), then it's not safe to perform diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll index a98d3f6ba9..5404cf57a5 100644 --- a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -3,7 +3,7 @@ ; CHECK: _f ; CHECK: adds ; CHECK-NOT: cmp -; CHECK: blxeq _g +; CHECK: blxeq _h define i32 @f(i32 %a, i32 %b) nounwind ssp { entry: @@ -12,11 +12,30 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @g(i32 %a, i32 %b) nounwind + tail call void (...)* @h(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry ret i32 %add } -declare void @g(...) +; CHECK: _g +; CHECK: orrs +; CHECK-NOT: cmp +; CHECK: blxeq _h + +define i32 @g(i32 %a, i32 %b) nounwind ssp { +entry: + %add = or i32 %b, %a + %cmp = icmp eq i32 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @h(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %add +} + +declare void @h(...) |