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authorChris Lattner <sabre@nondot.org>2004-08-15 23:07:40 +0000
committerChris Lattner <sabre@nondot.org>2004-08-15 23:07:40 +0000
commit105a56ac6b43ac38a5e2a692ed04bba6f7b7b677 (patch)
treee96496eb430abdd9f92a39417b8262ff556a832e
parentdd43e3493a8792db22b4f35423bfe3d909a2cfc4 (diff)
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V8 never used the instrselectorgenerator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15791 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Sparc/Makefile6
-rw-r--r--lib/Target/SparcV8/Makefile6
2 files changed, 2 insertions, 10 deletions
diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile
index 78da738aa7..2c9e3413bf 100644
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@@ -16,7 +16,7 @@ TDFILE := $(SourceDir)/SparcV8.td
# Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
- SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
+ SparcV8GenInstrInfo.inc
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen"
@@ -38,9 +38,5 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
-SparcV8GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building SparcV8.td instruction selector with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-selector -o $@
-
clean::
$(VERB) rm -f *.inc
diff --git a/lib/Target/SparcV8/Makefile b/lib/Target/SparcV8/Makefile
index 78da738aa7..2c9e3413bf 100644
--- a/lib/Target/SparcV8/Makefile
+++ b/lib/Target/SparcV8/Makefile
@@ -16,7 +16,7 @@ TDFILE := $(SourceDir)/SparcV8.td
# Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
- SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
+ SparcV8GenInstrInfo.inc
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen"
@@ -38,9 +38,5 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
-SparcV8GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
- @echo "Building SparcV8.td instruction selector with tblgen"
- $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-selector -o $@
-
clean::
$(VERB) rm -f *.inc