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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-29 03:17:01 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-29 03:17:01 +0000 |
| commit | 11fd5c0cd989010a2dfa59c75e3d5a5d2a970300 (patch) | |
| tree | e8e7e5dbac2966456b7fade8e301528459b6d08d | |
| parent | a6d7345ec91e4b07671f62d231e7c42f054bc70d (diff) | |
| download | llvm-11fd5c0cd989010a2dfa59c75e3d5a5d2a970300.tar.gz llvm-11fd5c0cd989010a2dfa59c75e3d5a5d2a970300.tar.bz2 llvm-11fd5c0cd989010a2dfa59c75e3d5a5d2a970300.tar.xz | |
Dwarf register 0 is r0, remove incorrect entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132276 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 6740820202..58cd543d0b 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -261,7 +261,7 @@ def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>; // Carry bit. In the architecture this is really bit 0 of the XER register // (which really is SPR register 1); this is the only bit interesting to a // compiler. -def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>; +def CARRY: SPR<1, "ca">; // FP rounding mode: bits 30 and 31 of the FP status and control register // This is not allocated as a normal register; it appears only in @@ -271,7 +271,7 @@ def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>; // return and call instructions are described as Uses of RM, so instructions // that do nothing but change RM will not get deleted. // Also, in the architecture it is not really a SPR; 512 is arbitrary. -def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>; +def RM: SPR<512, "**ROUNDING MODE**">; /// Register classes // Allocate volatiles first |