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| author | Jim Grosbach <grosbach@apple.com> | 2011-03-11 20:18:05 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-03-11 20:18:05 +0000 |
| commit | 1558df79b4b2b6558c6d107b62e4dab2564bd793 (patch) | |
| tree | da64b6891ca86b463fba96e3bd385b7d4c3be993 | |
| parent | f0112a224ffcb6df3044ebb601437ba8ce5b033c (diff) | |
| download | llvm-1558df79b4b2b6558c6d107b62e4dab2564bd793.tar.gz llvm-1558df79b4b2b6558c6d107b62e4dab2564bd793.tar.bz2 llvm-1558df79b4b2b6558c6d107b62e4dab2564bd793.tar.xz | |
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 4 | ||||
| -rw-r--r-- | utils/TableGen/ARMDecoderEmitter.cpp | 7 |
2 files changed, 2 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index d860a1416c..a80df2b410 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -4591,12 +4591,12 @@ class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>; def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>; def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>; -def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>; +def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>; def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>; def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>; def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>; -def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>; +def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>; // VREV32 : Vector Reverse elements within 32-bit words diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index 915f905ba1..dd8e3455d6 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -1654,13 +1654,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf") return false; - // Vector Reverse is similar to Vector Extract. There is no distinction - // between data types, other than size. - // - // VREV64df is equivalent to VREV64d32. - // VREV64qf is equivalent to VREV64q32. - if (Name == "VREV64df" || Name == "VREV64qf") return false; - // VDUPLNfd is equivalent to VDUPLN32d. // VDUPLNfq is equivalent to VDUPLN32q. // VLD1df is equivalent to VLD1d32. |