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| author | Tim Northover <tnorthover@apple.com> | 2014-04-28 11:27:43 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-28 11:27:43 +0000 |
| commit | 16aac4387f3ff3e8e8702b09ac23a0b320b3b1d3 (patch) | |
| tree | 9a6985d98ade490649164d1410f9cc501899db82 | |
| parent | db0b52c8e09e7cbb3452d4560dfeb1c933034794 (diff) | |
| download | llvm-16aac4387f3ff3e8e8702b09ac23a0b320b3b1d3.tar.gz llvm-16aac4387f3ff3e8e8702b09ac23a0b320b3b1d3.tar.bz2 llvm-16aac4387f3ff3e8e8702b09ac23a0b320b3b1d3.tar.xz | |
ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.
Someone couldn't bear to have a completely orthogonal set of floating-point
registers, so we've got some instructions that only accept v0-v15 (coming in
ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...).
Anyway, we were permitting even the out of range registers during assembly
(CodeGen handled it correctly). This adds a diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207412 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM64/ARM64RegisterInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 9 | ||||
| -rw-r--r-- | test/MC/ARM64/v128_lo-diagnostics.s | 11 |
3 files changed, 25 insertions, 1 deletions
diff --git a/lib/Target/ARM64/ARM64RegisterInfo.td b/lib/Target/ARM64/ARM64RegisterInfo.td index 514ba07bb0..3a8e969a01 100644 --- a/lib/Target/ARM64/ARM64RegisterInfo.td +++ b/lib/Target/ARM64/ARM64RegisterInfo.td @@ -431,7 +431,11 @@ def VectorRegAsmOperand : AsmOperandClass { let Name = "VectorReg"; } let ParserMatchClass = VectorRegAsmOperand in { def V64 : RegisterOperand<FPR64, "printVRegOperand">; def V128 : RegisterOperand<FPR128, "printVRegOperand">; -def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand">; +} + +def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; } +def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> { + let ParserMatchClass = VectorRegLoAsmOperand; } class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind> diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index 5fe0acc59d..71cf100daf 100644 --- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -688,6 +688,10 @@ public: } bool isReg() const { return Kind == k_Register && !Reg.isVector; } bool isVectorReg() const { return Kind == k_Register && Reg.isVector; } + bool isVectorRegLo() const { + return Kind == k_Register && Reg.isVector && + ARM64MCRegisterClasses[ARM64::FPR128_loRegClassID].contains(Reg.RegNum); + } /// Is this a vector list with the type implicit (presumably attached to the /// instruction itself)? @@ -1059,6 +1063,11 @@ public: Inst.addOperand(MCOperand::CreateReg(getReg())); } + void addVectorRegLoOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateReg(getReg())); + } + template <unsigned NumRegs> void addVectorList64Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); diff --git a/test/MC/ARM64/v128_lo-diagnostics.s b/test/MC/ARM64/v128_lo-diagnostics.s new file mode 100644 index 0000000000..ffe29cfbed --- /dev/null +++ b/test/MC/ARM64/v128_lo-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null +// RUN: FileCheck %s < %t + + sqrdmulh v0.8h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqrdmulh h0, h1, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqdmull2 v0.4h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction |