Test case hygiene.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176772 91177308-0d34-0410-b5e6-96231b3b80d8

18 files changed, 50 insertions, 51 deletions

diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll
index 9dddf74dd0..c66aa5bfc5 100644
--- a/test/CodeGen/AArch64/callee-save.ll
+++ b/test/CodeGen/AArch64/callee-save.ll
@@ -5,10 +5,10 @@
 define void @foo() {
 ; CHECK: foo:
 
-; CHECK stp d14, d15, [sp
-; CHECK stp d12, d13, [sp
-; CHECK stp d10, d11, [sp
-; CHECK stp d8, d9, [sp
+; CHECK: stp d14, d15, [sp
+; CHECK: stp d12, d13, [sp
+; CHECK: stp d10, d11, [sp
+; CHECK: stp d8, d9, [sp
 
   ; Create lots of live variables to exhaust the supply of
   ; caller-saved registers
diff --git a/test/CodeGen/AArch64/fastcc-reserved.ll b/test/CodeGen/AArch64/fastcc-reserved.ll
index 1a114a5dc4..e40aa3033b 100644
--- a/test/CodeGen/AArch64/fastcc-reserved.ll
+++ b/test/CodeGen/AArch64/fastcc-reserved.ll
@@ -13,7 +13,7 @@ define fastcc void @foo(i32 %in) {
 
 ; Normal frame setup stuff:
 ; CHECK: sub sp, sp,
-; CHECK stp x29, x30
+; CHECK: stp x29, x30
 
 ; Reserve space for call-frame:
 ; CHECK: sub sp, sp, #16
@@ -38,17 +38,17 @@ define void @foo1(i32 %in) {
 
   %addr = alloca i8, i32 %in
 ; Normal frame setup again
-; CHECK sub sp, sp,
-; CHECK stp x29, x30
+; CHECK: sub sp, sp,
+; CHECK: stp x29, x30
 
 ; Reserve space for call-frame
-; CHECK sub sp, sp, #16
+; CHECK: sub sp, sp, #16
 
   call void @wont_pop([8 x i32] undef, i32 42)
-; CHECK bl wont_pop
+; CHECK: bl wont_pop
 
 ; This time we *do* need to unreserve the call-frame
-; CHECK add sp, sp, #16
+; CHECK: add sp, sp, #16
 
 ; Check for epilogue (primarily to make sure sp spotted above wasn't
 ; part of it).
diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll
index 5675e5a1f9..78fde6a3c3 100644
--- a/test/CodeGen/AArch64/func-argpassing.ll
+++ b/test/CodeGen/AArch64/func-argpassing.ll
@@ -44,7 +44,7 @@ define void @take_struct(%myStruct* byval %structval) {
     %val1 = load i64* %addr1
 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
     store i64 %val1, i64* @var64
-; CHECK str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
+; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
 
     ret void
 }
@@ -66,7 +66,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
     %val1 = load i64* %addr1
 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
     store i64 %val1, i64* @var64
-; CHECK str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
+; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
 
     ret void
 }
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index abb09a5e53..13b689c408 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -61,7 +61,7 @@ define void @simple_rets() {
 
   call void @return_large_struct(%myStruct* sret @varstruct)
 ; CHECK: add x8, {{x[0-9]+}}, #:lo12:varstruct
-; CHECK bl return_large_struct
+; CHECK: bl return_large_struct
 
   ret void
 }
@@ -93,7 +93,7 @@ define void @check_stack_args() {
 ; CHECK: ldr s[[STACKEDREG:[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI
 ; CHECK: mov x0, sp
 ; CHECK: str d[[STACKEDREG]], [x0]
-; CHECK bl stacked_fpu
+; CHECK: bl stacked_fpu
   ret void
 }
 
diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll
index afdf681c28..b8a5fb9322 100644
--- a/test/CodeGen/AArch64/movw-consts.ll
+++ b/test/CodeGen/AArch64/movw-consts.ll
@@ -75,7 +75,7 @@ define i64 @test10() {
 
 define void @test11() {
 ; CHECK: test11:
-; CHECK movz {{w[0-9]+}}, #0
+; CHECK: mov {{w[0-9]+}}, wzr
   store i32 0, i32* @var32
   ret void
 }
diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
index 5c97a0229f..980e2ffef9 100644
--- a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
+++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
@@ -5,7 +5,7 @@ declare void @bar()
 
 define void @test_w29_reserved() {
 ; CHECK: test_w29_reserved:
-; CHECK add x29, sp, #{{[0-9]+}}
+; CHECK: add x29, sp, #{{[0-9]+}}
 
   %val1 = load volatile i32* @var
   %val2 = load volatile i32* @var
diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll
index 94edff5c0b..58fbbda0f6 100644
--- a/test/CodeGen/ARM/call-tc.ll
+++ b/test/CodeGen/ARM/call-tc.ll
@@ -103,7 +103,6 @@ define i32 @t8(i32 %x) nounwind ssp {
 entry:
 ; CHECKT2D: t8:
 ; CHECKT2D-NOT: push
-; CHECKT2D-NOT
   %and = and i32 %x, 1
   %tobool = icmp eq i32 %and, 0
   br i1 %tobool, label %if.end, label %if.then
diff --git a/test/CodeGen/ARM/ehabi-filters.ll b/test/CodeGen/ARM/ehabi-filters.ll
index d15aa7b32c..c42839d9fe 100644
--- a/test/CodeGen/ARM/ehabi-filters.ll
+++ b/test/CodeGen/ARM/ehabi-filters.ll
@@ -15,7 +15,7 @@ declare void @__cxa_throw(i8*, i8*, i8*)
 declare void @__cxa_call_unexpected(i8*)
 
 define i32 @main() {
-; CHECK main:
+; CHECK: main:
 entry:
   %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
   %0 = bitcast i8* %exception.i to i32*
diff --git a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
index e8cc2b238d..0b5267ddc9 100644
--- a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
+++ b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
@@ -103,7 +103,7 @@ entry:
 ; ARM: t11
   %add.ptr = getelementptr inbounds i16* %a, i64 8
   store i16 0, i16* %add.ptr, align 2
-; ARM strh r{{[1-9]}}, [r0, #16]
+; ARM: strh r{{[1-9]}}, [r0, #16]
   ret void
 }
 
diff --git a/test/CodeGen/Mips/jtstat.ll b/test/CodeGen/Mips/jtstat.ll
index 6c1eb8db6b..01afc080c2 100644
--- a/test/CodeGen/Mips/jtstat.ll
+++ b/test/CodeGen/Mips/jtstat.ll
@@ -56,8 +56,8 @@ sw.epilog:                                        ; preds = %entry, %sw.bb7, %sw
   ret void
 }
 
-; CHECK-STATIC16 	li	${{[0-9]+}}, %hi($JTI{{[0-9]+}}_{{[0-9]+}})
-; CHECK-STATIC16 	lw	${{[0-9]+}}, %lo($JTI{{[0-9]+}}_{{[0-9]+}})({{[0-9]+}})
+; CHECK-STATIC16: li	${{[0-9]+}}, %hi($JTI{{[0-9]+}}_{{[0-9]+}})
+; CHECK-STATIC16: lw	${{[0-9]+}}, %lo($JTI{{[0-9]+}}_{{[0-9]+}})(${{[0-9]+}})
 ; CHECK-STATIC16: $JTI{{[0-9]+}}_{{[0-9]+}}:
 ; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}})
 ; CHECK-STATIC16: .4byte ($BB0_{{[0-9]+}})
diff --git a/test/CodeGen/Mips/mips64-libcall.ll b/test/CodeGen/Mips/mips64-libcall.ll
index c53ccfde51..d54598be70 100644
--- a/test/CodeGen/Mips/mips64-libcall.ll
+++ b/test/CodeGen/Mips/mips64-libcall.ll
@@ -5,7 +5,7 @@
 
 ; Check that %add is not passed in an integer register.
 ;
-; HARD    : callfloor:
+; HARD: callfloor:
 ; HARD-NOT: dmfc1 $4
 
 define double @callfloor(double %d) nounwind readnone {
diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll
index 3180f464d1..eb41667610 100644
--- a/test/CodeGen/PowerPC/vec_cmp.ll
+++ b/test/CodeGen/PowerPC/vec_cmp.ll
@@ -54,7 +54,7 @@ entry:
 }
 ; CHECK:     v16si8_cmp_ne:
 ; CHECK:     vcmpequb [[RET:[0-9]+]], 2, 3
-; CHECK-NOR: vnor     2, [[RET]], [[RET]]
+; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
 define <16 x i8> @v16si8_cmp_le(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
 entry:
diff --git a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
index aad44d9edf..71705a64f5 100644
--- a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
+++ b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
@@ -4,7 +4,7 @@
 ;to a SETNE_INT.  There should only be one SETNE_INT instruction.
 
 ;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK_NOT: SETNE_INT
+;CHECK-NOT: SETNE_INT
 
 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll
index be62342986..e69f64e0e1 100644
--- a/test/CodeGen/R600/literals.ll
+++ b/test/CodeGen/R600/literals.ll
@@ -6,7 +6,7 @@
 ; or
 ; ADD_INT literal.x REG, 5
 
-; CHECK; @i32_literal
+; CHECK: @i32_literal
 ; CHECK: ADD_INT {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} 5
 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
 entry:
diff --git a/test/CodeGen/X86/fp-fast.ll b/test/CodeGen/X86/fp-fast.ll
index d70aa7d79f..287504801d 100644
--- a/test/CodeGen/X86/fp-fast.ll
+++ b/test/CodeGen/X86/fp-fast.ll
@@ -38,7 +38,7 @@ define float @test3(float %a) {
 ; CHECK: test4
 define float @test4(float %a) {
 ; CHECK-NOT: fma
-; CHECK-NOT mul
+; CHECK-NOT: mul
 ; CHECK-NOT: add
 ; CHECK: ret
   %t1 = fmul float %a, 0.0
diff --git a/test/CodeGen/X86/vec_sdiv_to_shift.ll b/test/CodeGen/X86/vec_sdiv_to_shift.ll
index 35e052d97b..349868a87f 100644
--- a/test/CodeGen/X86/vec_sdiv_to_shift.ll
+++ b/test/CodeGen/X86/vec_sdiv_to_shift.ll
@@ -16,7 +16,7 @@ entry:
 define <4 x i32> @sdiv_zero(<4 x i32> %var) {
 entry:
 ; CHECK: sdiv_zero
-; CHECK-NOT sra
+; CHECK-NOT: sra
 ; CHECK: ret
   %0 = sdiv <4 x i32> %var, <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %0
diff --git a/test/Transforms/GlobalOpt/integer-bool.ll b/test/Transforms/GlobalOpt/integer-bool.ll
index cf025ec614..7a91a767a1 100644
--- a/test/Transforms/GlobalOpt/integer-bool.ll
+++ b/test/Transforms/GlobalOpt/integer-bool.ll
@@ -2,9 +2,9 @@
 ;; check that global opt turns integers that only hold 0 or 1 into bools.
 
 @G = internal addrspace(1) global i32 0
-; CHECK @G.b
-; CHECK addrspace(1)
-; CHECK global i1 0
+; CHECK: @G.b
+; CHECK: addrspace(1)
+; CHECK: global i1 0
 
 define void @set1() {
   store i32 0, i32 addrspace(1)* @G
@@ -19,7 +19,7 @@ define void @set2() {
 }
 
 define i1 @get() {
-; CHECK @get
+; CHECK: @get
   %A = load i32 addrspace(1) * @G
   %C = icmp slt i32 %A, 2
   ret i1 %C
diff --git a/test/Transforms/LoopVectorize/global_alias.ll b/test/Transforms/LoopVectorize/global_alias.ll
index 24e698bb21..121da8ba7e 100644
--- a/test/Transforms/LoopVectorize/global_alias.ll
+++ b/test/Transforms/LoopVectorize/global_alias.ll
@@ -24,7 +24,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; }
 ; CHECK: define i32 @noAlias01
 ; CHECK: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias01(i32 %a) nounwind {
 entry:
@@ -72,7 +72,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias02
 ; CHECK: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias02(i32 %a) {
 entry:
@@ -121,7 +121,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias03
 ; CHECK: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias03(i32 %a) {
 entry:
@@ -170,7 +170,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias04
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 ;
 ; TODO: This test vectorizes (with run-time check) on real targets with -O3)
 ; Check why it's not being vectorized even when forcing vectorization
@@ -224,7 +224,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias05
 ; CHECK: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias05(i32 %a) #0 {
 entry:
@@ -280,7 +280,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias06
 ; CHECK: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias06(i32 %a) #0 {
 entry:
@@ -337,7 +337,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias07
 ; CHECK: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias07(i32 %a) #0 {
 entry:
@@ -389,7 +389,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias08
 ; CHECK: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias08(i32 %a) #0 {
 entry:
@@ -441,7 +441,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias09
 ; CHECK: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias09(i32 %a) #0 {
 entry:
@@ -493,7 +493,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias10
 ; CHECK-NOT: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 ;
 ; TODO: This test vectorizes (with run-time check) on real targets with -O3)
 ; Check why it's not being vectorized even when forcing vectorization
@@ -553,7 +553,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias11
 ; CHECK: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias11(i32 %a) #0 {
 entry:
@@ -613,7 +613,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias12
 ; CHECK: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias12(i32 %a) #0 {
 entry:
@@ -674,7 +674,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias13
 ; CHECK: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias13(i32 %a) #0 {
 entry:
@@ -723,7 +723,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @noAlias14
 ; CHECK: sub nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @noAlias14(i32 %a) #0 {
 entry:
@@ -779,7 +779,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @mayAlias01
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @mayAlias01(i32 %a) nounwind {
 entry:
@@ -829,7 +829,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @mayAlias02
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @mayAlias02(i32 %a) nounwind {
 entry:
@@ -879,7 +879,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @mayAlias03
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @mayAlias03(i32 %a) nounwind {
 entry:
@@ -936,7 +936,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @mustAlias01
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @mustAlias01(i32 %a) nounwind {
 entry:
@@ -986,7 +986,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @mustAlias02
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @mustAlias02(i32 %a) nounwind {
 entry:
@@ -1035,7 +1035,7 @@ for.end:                                          ; preds = %for.cond
 ; }
 ; CHECK: define i32 @mustAlias03
 ; CHECK-NOT: add nsw <4 x i32>
-; CHECK ret
+; CHECK: ret
 
 define i32 @mustAlias03(i32 %a) nounwind {
 entry: