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| author | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:46 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:46 +0000 |
| commit | 1d98530196feee3b1b3ddcd793377b9b430a411e (patch) | |
| tree | a9761b4c5e36efa1c638d35d662a2c2f49d636b3 | |
| parent | f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa (diff) | |
| download | llvm-1d98530196feee3b1b3ddcd793377b9b430a411e.tar.gz llvm-1d98530196feee3b1b3ddcd793377b9b430a411e.tar.bz2 llvm-1d98530196feee3b1b3ddcd793377b9b430a411e.tar.xz | |
X86 itinerary properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86Schedule.td | 24 | ||||
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 7 |
2 files changed, 29 insertions, 2 deletions
diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index f670f28b44..4331cf31e8 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -456,6 +456,28 @@ def IIC_NOP : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. -def GenericItineraries : ProcessorItineraries<[], [], []>; +// IssueWidth is analagous to the number of decode units. Core and its +// descendents, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are bufferred +// so adjacent micro-ops don't directly compete. +// +// MinLatency=0 indicates that RAW dependencies can be decoded in the +// same cycle. +// +// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef +// indicates high latency opcodes. Alternatively, InstrItinData +// entries may be included here to define specific operand +// latencies. Since these latencies are not used for pipeline hazards, +// they do not need to be exact. +// +// This set of instruction itineraries should contain no reference to +// InstrStages. When an iterary has no stages, the scheduler can +// bypass the logic needed for checking pipeline stage hazards. +def GenericItineraries : MultiIssueItineraries< + 4, // IssueWidth + 0, // MinLatency + 4, // LoadLatency (expected, may be overriden by OperandCycles) + 10, // HighLatency (expected, may be overriden by OperandCycles) + [], [], []>; // no FuncUnits, Bypasses, or InstrItinData. include "X86ScheduleAtom.td" diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 81530b5f1f..56dd3407b2 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -22,7 +22,12 @@ def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA // SIMD/FP: SIMD ALU, FP Adder -def AtomItineraries : ProcessorItineraries< +def AtomItineraries : MultiIssueItineraries< + 2, // IssueWidth=2 allows 2 instructions per scheduling group. + 1, // MinLatency=1. InstrStage cycles overrides MinLatency. + // OperandCycles may be used for expected latency. + 3, // LoadLatency (expected, may be overriden by OperandCycles) + 30,// HighLatency (expected, may be overriden by OperandCycles) [ Port0, Port1 ], [], [ // P0 only |